Discussion:
1 pps sync'ing
(too old to reply)
Martyn Smith
2018-06-29 13:13:10 UTC
Permalink
Hello,



My colleague Steve asked a question about wanting to generate a 10 MHz and
100 MHz squarewaves with both rising edges aligned to a reference 1 pps
input (to within 5ns).



We already have a product that can do this (at 10 MHz), but it is very
complicated, and Steve's job is to fine an easier approach.



I'm not trying to achieve 1-5 ns to UTC as that's not possible as already
pointed out, just 1 to 5 ns to a reference 1 pps (from Hydrogen Maser).



We definitely need all rising edges synchronised. Of course, we will have
to be very careful with cabling lengths etc otherwise we will lose all this
synchronisation.



So starting at 100 MHz and dividing down is a good idea, except the 100 MHz
needs to be synchronised in the first place, which brings me back to the
first problem.



Our existing product generates 48 bit BCD time code all synchronised to a 1
pps inputs. This was designed ages ago for a customer. So, the last bit of
the 48 bit is 100ns in time or 10 MHz in frequency.



So we could use this board and then lock the 100 MHz to the 10 MHz.



But it's not very elegant!!



Anyway, the research continues.



Best Regards



Martyn



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Chris Caudle
2018-06-29 13:51:21 UTC
Permalink
Post by Martyn Smith
My colleague Steve asked a question about wanting to
generate a 10 MHz and 100 MHz squarewaves with
both rising edges aligned to a reference 1 pps
input (to within 5ns).
You say "both," but which edge you pick is a little bit arbitrary since
there are 100 million to choose to align to the PPS.

General approach could be something like this (probably not optimal, but
simple to understand):
100MHz tuneable oscillator -> divide by 10 -> 10MHz
10MHz -> divide by 10M -> 1Hz

So you now have 100MHz, 10MHz, and 1Hz, syntonized since they came from
the same source, but the synchronization is offset by the delay through
the divider chains.
Take the 10MHz and 1Hz signals, and send them to the data input of a D
flip-flop, clocked by the 100MHz, and now the 100MHz, 10MHz, and 1Hz edges
are offset only by the delay through the flip-flop.
You would still have to be careful in part selection, standard CMOS logic
would have several ns of propagation delay, so you couldn't just grab any
random flip-flop and guarantee 5ns edge alignment.

If you want to throw a little money and layout effort at the problem
Analog Devices make a device which specifically advertise as being able to
synchronize clock outputs to 1PPS input:

http://www.analog.com/en/products/clock-and-timing/clock-generation-distribution/clock-synchronization/ad9548.html

http://www.analog.com/en/education/education-library/videos/756421501001.html

That device is basically a DDS based clock generator with digital PLL all
in a single package, so could be more than needed for this task. I have
not used the AD part personally yet, I noticed it while looking for
something else and thought the fact they specifically pointed out it was
useful for synchronizing to PPS was interesting.
--
Chris Caudle




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Chris Caudle
2018-06-29 14:20:04 UTC
Permalink
Sorry, got distracted part way through this email and left out an
Post by Chris Caudle
100MHz tuneable oscillator -> divide by 10 -> 10MHz
10MHz -> divide by 10M -> 1Hz
...data input of a D flip-flop, clocked by the 100MHz,
and now the 100MHz, 10MHz, and 1Hz edges
are offset only by the delay through the flip-flop.
After you have three clock signals synchronized to each other, you still
have to steer to line up with your input PPS signal. You will have to
build a PLL to compare your generated 1Hz clock and the input PPS and
steer the 100MHz oscillator to keep them lined up. You would also want
some logic to control the reset on the dividers to get the signals started
out close to lined up with the input PPS or it might take a very long time
to achieve lock.

That is where having something like the Analog Devices part (or similar
Silicon Labs, Microsemi, etc.) are useful, they save the problems of
designing the digital PLL.
--
Chris Caudle




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Lester Veenstra
2018-06-29 14:10:19 UTC
Permalink
Martin:
Are you with PTS in Littleton ?

Lester B Veenstra K1YCM MØYCM W8YCM 6Y6Y
***@veenstras.com

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-----Original Message-----
From: time-nuts [mailto:time-nuts-***@lists.febo.com] On Behalf Of Martyn Smith
Sent: Friday, June 29, 2018 9:13 AM
To: time-***@febo.com
Subject: [time-nuts] 1 pps sync'ing

Hello,



My colleague Steve asked a question about wanting to generate a 10 MHz and
100 MHz squarewaves with both rising edges aligned to a reference 1 pps input (to within 5ns).



We already have a product that can do this (at 10 MHz), but it is very complicated, and Steve's job is to fine an easier approach.



I'm not trying to achieve 1-5 ns to UTC as that's not possible as already pointed out, just 1 to 5 ns to a reference 1 pps (from Hydrogen Maser).



We definitely need all rising edges synchronised. Of course, we will have to be very careful with cabling lengths etc otherwise we will lose all this synchronisation.



So starting at 100 MHz and dividing down is a good idea, except the 100 MHz needs to be synchronised in the first place, which brings me back to the first problem.



Our existing product generates 48 bit BCD time code all synchronised to a 1 pps inputs. This was designed ages ago for a customer. So, the last bit of the 48 bit is 100ns in time or 10 MHz in frequency.



So we could use this board and then lock the 100 MHz to the 10 MHz.



But it's not very elegant!!



Anyway, the research continues.



Best Regards



Martyn



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Attila Kinali
2018-06-29 14:37:41 UTC
Permalink
On Fri, 29 Jun 2018 14:13:10 +0100
Post by Martyn Smith
I'm not trying to achieve 1-5 ns to UTC as that's not possible as already
pointed out, just 1 to 5 ns to a reference 1 pps (from Hydrogen Maser).
How about just using an FPGA then? If you clock it at 200-400MHz,
then you can built a digital phase stepper with 2.5-5ns step size.
The FPGA can also handle the synchronization to an external pulse
quite easily and do fault detection (like the pulse suddenly jumping)
etc pp.

Disadvantage of this is, that the output of an FPGA is rather noisy.
Ie you will not get very low phase noise/jitter, but depending on your
specs, it might be actually enough. If you need lower phase noise,
you'd need to add a D-flipflop outside of the FPGA to syncrhonize
the output. If done right, this give a jitter in the order of 100-200fs.
Post by Martyn Smith
We definitely need all rising edges synchronised. Of course, we will have
to be very careful with cabling lengths etc otherwise we will lose all this
synchronisation.
Cable length of 1m is somewhere in the order of 6-7ns delay. You have to
be careful with lengths, but not very much so. If the cables are matched
up to 1-2cm, that should be enough.

Attila Kinali
--
It is upon moral qualities that a society is ultimately founded. All
the prosperity and technological sophistication in the world is of no
use without that foundation.
-- Miss Matheson, The Diamond Age, Neil Stephenson
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Attila Kinali
2018-06-29 14:45:02 UTC
Permalink
On Fri, 29 Jun 2018 16:37:41 +0200
Post by Attila Kinali
How about just using an FPGA then? If you clock it at 200-400MHz,
then you can built a digital phase stepper with 2.5-5ns step size.
The FPGA can also handle the synchronization to an external pulse
quite easily and do fault detection (like the pulse suddenly jumping)
etc pp.
BTW: if you have local oscillators for 10MHz and 100MHz, then it's
also possible to sync them up, by measuring their relative phase.
But all that becomes more complicated. In the end, it depends on
what the exact specs are, that you need to achieve and how much
effort you want to spend. As your PPS signal is fairly stable,
it should be doable to sync everything up to better than 10ps
(limited by how accurately the phase can be measured).

If you want to, you can contact me off-list for more in-depth discussion.

Attila Kinali
--
It is upon moral qualities that a society is ultimately founded. All
the prosperity and technological sophistication in the world is of no
use without that foundation.
-- Miss Matheson, The Diamond Age, Neil Stephenson
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jimlux
2018-06-29 14:42:31 UTC
Permalink
Post by Martyn Smith
Hello,
My colleague Steve asked a question about wanting to generate a 10 MHz and
100 MHz squarewaves with both rising edges aligned to a reference 1 pps
input (to within 5ns).
Your 1pps to 10MHz sync is complex and you want to avoid it?

Otherwise, a x10 multiplier will generate a 100MHz from 10 MHz that is
coherent (leaving aside issues of squaring up sine waves, etc.). There
will be some time offset between the zero crossing of 100 and zero
crossing of 10, but that should be "adjustable" by any of a variety of
means (10ns is a couple meters of coax). It will vary with temperature
somewhat.

The x10 is usually done as a x5 and a x2. I guess a PLL multiplier would
also work.

Other than that, some scheme where you generate your 100, divide to get
10, and adjust the 100 a bit to line it up with the 1pps. (unless your
tolerance spec is +/- 5ns, in which case you just use the 100 to latch
the 1pps).




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Bob kb8tq
2018-06-29 14:45:20 UTC
Permalink
Hi

If the 1 PPS is from something like a Maser ( so it’s not all over the place)
*and* the 100 MHz is from something like an OCXO (so it also is reasonably
stable), this all gets down to PLL design.

Since it’s 1 pps in, you need a process that will resolve the input phase
reliably to << 1 ns. That is not trivial, but it can be done. You also need
a stable way to get from 100 MHz to 1 pps. The “just do it with an
FPGA” does not cover all the issues there…. there are a number of
delays that are going to vary.

Once you have that worked out, there *will* be some time period over
which you will achieve your 1 ns number to some level of confidence.
There will never be an absolute guarantee.

Bob
Post by Martyn Smith
Hello,
My colleague Steve asked a question about wanting to generate a 10 MHz and
100 MHz squarewaves with both rising edges aligned to a reference 1 pps
input (to within 5ns).
We already have a product that can do this (at 10 MHz), but it is very
complicated, and Steve's job is to fine an easier approach.
I'm not trying to achieve 1-5 ns to UTC as that's not possible as already
pointed out, just 1 to 5 ns to a reference 1 pps (from Hydrogen Maser).
We definitely need all rising edges synchronised. Of course, we will have
to be very careful with cabling lengths etc otherwise we will lose all this
synchronisation.
So starting at 100 MHz and dividing down is a good idea, except the 100 MHz
needs to be synchronised in the first place, which brings me back to the
first problem.
Our existing product generates 48 bit BCD time code all synchronised to a 1
pps inputs. This was designed ages ago for a customer. So, the last bit of
the 48 bit is 100ns in time or 10 MHz in frequency.
So we could use this board and then lock the 100 MHz to the 10 MHz.
But it's not very elegant!!
Anyway, the research continues.
Best Regards
Martyn
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Artek Manuals
2018-06-29 15:12:38 UTC
Permalink
Maybe I am missing something obvious here but after using the 1PPS/10MHz
reference multiplied up to 100 MHz cant you just insert a passive L/C
phase shift network at the input (or output) of the multiplier chain and
tune one of the "C" legs in the phase shift network to align the  edges
(change the the delay slightly) of the two waveforms? Temperature
stability of the phase shift network might be a problem ? What are the
other drawbacks of this simple approach?

-DC
Post by Martyn Smith
Hello,
My colleague Steve asked a question about wanting to generate a 10 MHz and
100 MHz squarewaves with both rising edges aligned to a reference 1 pps
input (to within 5ns).
--
Dave
***@ArtekManuals.com
www.ArtekManuals.com


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Dana Whitlow
2018-06-29 15:28:59 UTC
Permalink
I might point out that bringing the edges into final alignment might most
easily be
accomplished with coaxial lines trimmed to the right lengths. At most the
line for
10 MHz would need to be ~66 feet long (assuming the usual 66% VF for
polyethylene
dielectric), and the worst case length for the 100 MHz signal would be
under ~7 feet.

I suspect that the logic circuitry (and possibly the delay lines) for this
project may
need some degree of temperature stabilization as well, in order to maintain
the
desired alignment accuracy over time.

Dana Whitlow
Post by Artek Manuals
Maybe I am missing something obvious here but after using the 1PPS/10MHz
reference multiplied up to 100 MHz cant you just insert a passive L/C phase
shift network at the input (or output) of the multiplier chain and tune one
of the "C" legs in the phase shift network to align the edges (change the
the delay slightly) of the two waveforms? Temperature stability of the
phase shift network might be a problem ? What are the other drawbacks of
this simple approach?
-DC
Post by Martyn Smith
Hello,
My colleague Steve asked a question about wanting to generate a 10 MHz and
100 MHz squarewaves with both rising edges aligned to a reference 1 pps
input (to within 5ns).
--
Dave
www.ArtekManuals.com
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Martyn Smith
2018-06-30 09:29:08 UTC
Permalink
Hello,

Just want to say thank you to all your replies to my 1 pps 100/10MHz/1 pps question.

Food for thought.

Someone asked who we are. We are an English company manufacturing distribution amplifiers and frequency standards.

Don't mean to advertise (well maybe I do), but I am answering someone else's questions. Obviously contact me offline for any more info.

Martyn (G8GMH, KS6AQL but no longer active)

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