Discussion:
White Rabbit time distribution performance
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Mattia Rizzi
2018-07-02 19:37:53 UTC
Permalink
Hello!
I published a paper on WR time distribution performance that you might
consider interesting. It's available at IEEExplorer:
https://ieeexplore.ieee.org/document/8400550/

Abstract:
This article investigates the ultimate limits of White Rabbit (WR), an
high-accuracy time distribution system based on FPGA. The knowledge of such
limits is essential for new emerging applications that are evaluating WR.
In this article, we identify and study the key elements in the WR
synchronization: the Digital Dual Mixer Time Difference phase detector and
the Gigabit Ethernet transceiver. The benchmarks and experimental analysis
of these key elements allow us to determine the WR Switch performance
limits and evaluate their evolution with newer FPGAs. The identified
performance limits are achievable by the present-day generation of WR
Switch. The ultimate limits of short-term synchronization performance due
to FPGA implementation have been derived through analysis and then
demonstrated using the existing WR Switch enhanced with an additional
daughter-board. This combination (WR Switch and daughter-board) achieves a
tenfold improvement in terms of phase noise, jitter and shortterm stability
with respect to the current WR performance. Both phase detectors and
Gigabit transceivers have a similar phase noise contribution equal to a
short-term stability of MDEV 4E-13 at τ=1 s (dominated by flicker PM noise).

cheers
Mattia
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Arnold Tibus
2018-07-02 20:51:24 UTC
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Thank you very much Mattia -
I am interested to read and to learn - but I see:
"Sign in or purchase", not loved by everybody, and I have no membership,
a pity, sorry.

My best wishes,

Arnold, DK2WT
Post by Mattia Rizzi
Hello!
I published a paper on WR time distribution performance that you might
https://ieeexplore.ieee.org/document/8400550/
This article investigates the ultimate limits of White Rabbit (WR), an
high-accuracy time distribution system based on FPGA. The knowledge of such
limits is essential for new emerging applications that are evaluating WR.
In this article, we identify and study the key elements in the WR
synchronization: the Digital Dual Mixer Time Difference phase detector and
the Gigabit Ethernet transceiver. The benchmarks and experimental analysis
of these key elements allow us to determine the WR Switch performance
limits and evaluate their evolution with newer FPGAs. The identified
performance limits are achievable by the present-day generation of WR
Switch. The ultimate limits of short-term synchronization performance due
to FPGA implementation have been derived through analysis and then
demonstrated using the existing WR Switch enhanced with an additional
daughter-board. This combination (WR Switch and daughter-board) achieves a
tenfold improvement in terms of phase noise, jitter and shortterm stability
with respect to the current WR performance. Both phase detectors and
Gigabit transceivers have a similar phase noise contribution equal to a
short-term stability of MDEV 4E-13 at τ=1 s (dominated by flicker PM noise).
cheers
Mattia
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_______________________________________________
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