timing and RTL-SDR
(too old to reply)
2018-04-13 22:24:06 UTC
the behavior of the inside of the 2832 downconverter isn't documented,
although there's some theorizing that it's a complex I/Q multiply,
followed by a FIR filter with 31 taps (which are published), followed by
a resampler/decimator followed by a decimate by 4.

So I experimented with feeding in a step function to this and sliding it
over. 10 MHz LO, 1 MHz output frequency (so the rational resampler is
5/36).. I used Octave's resample() and decimate() and ran it floating
point, so who knows if that's what the part actually does. But, it does
start to look like what I'm seeing.

I also (based on the discussion of Jim Palfreyman's quasar) doing a find
the peaks do a linear fit and then stack.