Discussion:
10 MHz -> 16 MHz
(too old to reply)
Tom Van Baak
2018-09-30 03:57:14 UTC
Permalink
What's a clever, simple, reliable (pick 2 of 3) way to get 16 MHz out of 10 MHz? Low phase noise isn't a big requirement and jitter doesn't need to be sub-nanosecond. The main requirement is perfect cycle count accuracy. This is for driving a 16 MHz microcontroller from a 10 MHz Rb/Cs/GPSDO. 10 MHz input is likely sine; 16 MHz output is 3v3 or 5v CMOS.

Thanks,
/tvb


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Mike Feher
2018-09-30 04:08:39 UTC
Permalink
I do not know about clever, but, how about a doubler then a divide by five
and the mix the 20 with the 4 to get 16 with a few filters in between. -
Mike



Mike B. Feher, N4FS

89 Arnold Blvd.

Howell NJ 07731

848-245-9115



-----Original Message-----
From: time-nuts <time-nuts-***@lists.febo.com> On Behalf Of Tom Van Baak
Sent: Saturday, September 29, 2018 11:57 PM
To: Discussion of precise time and frequency measurement
<time-***@lists.febo.com>
Subject: [time-nuts] 10 MHz -> 16 MHz



What's a clever, simple, reliable (pick 2 of 3) way to get 16 MHz out of 10
MHz? Low phase noise isn't a big requirement and jitter doesn't need to be
sub-nanosecond. The main requirement is perfect cycle count accuracy. This
is for driving a 16 MHz microcontroller from a 10 MHz Rb/Cs/GPSDO. 10 MHz
input is likely sine; 16 MHz output is 3v3 or 5v CMOS.



Thanks,

/tvb





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Tom Miller
2018-09-30 05:25:31 UTC
Permalink
16 MHz VCO divided by 16 to 1 MHz; 10 MHz divided by 10; Phase detector and
loop filter to control the 16 MHz VCO.

Regards,
Tom



----- Original Message -----
From: "Tom Van Baak" <***@LeapSecond.com>
To: "Discussion of precise time and frequency measurement"
<time-***@lists.febo.com>
Sent: Saturday, September 29, 2018 11:57 PM
Subject: [time-nuts] 10 MHz -> 16 MHz
Post by Tom Van Baak
What's a clever, simple, reliable (pick 2 of 3) way to get 16 MHz out of
10 MHz? Low phase noise isn't a big requirement and jitter doesn't need to
be sub-nanosecond. The main requirement is perfect cycle count accuracy.
This is for driving a 16 MHz microcontroller from a 10 MHz Rb/Cs/GPSDO. 10
MHz input is likely sine; 16 MHz output is 3v3 or 5v CMOS.
Thanks,
/tvb
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Mike Cook
2018-09-30 05:58:50 UTC
Permalink
How about an ICS525 or ICS527. IDT’s calculator allows a 0 ppm frequency error. You would need a sine-square converter for input.
Post by Tom Van Baak
What's a clever, simple, reliable (pick 2 of 3) way to get 16 MHz out of 10 MHz? Low phase noise isn't a big requirement and jitter doesn't need to be sub-nanosecond. The main requirement is perfect cycle count accuracy. This is for driving a 16 MHz microcontroller from a 10 MHz Rb/Cs/GPSDO. 10 MHz input is likely sine; 16 MHz output is 3v3 or 5v CMOS.
Thanks,
/tvb
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Bruce Griffiths
2018-09-30 06:35:34 UTC
Permalink
Full wave rectify the sinewave input, extract the 8th Harmonic with a passive filter.
Drive the input of a divide by 5 circuit via a suitable impedance converter network.
Could even use a CMOS 74XX74 flipflop plus a few passive components as the divider.

Bruce
Post by Tom Van Baak
What's a clever, simple, reliable (pick 2 of 3) way to get 16 MHz out of 10 MHz? Low phase noise isn't a big requirement and jitter doesn't need to be sub-nanosecond. The main requirement is perfect cycle count accuracy. This is for driving a 16 MHz microcontroller from a 10 MHz Rb/Cs/GPSDO. 10 MHz input is likely sine; 16 MHz output is 3v3 or 5v CMOS.
Thanks,
/tvb
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Luca
2018-09-30 07:01:44 UTC
Permalink
Simple 100 kHz ref frequency PLL (like old cmos series) with 16 MHz VCXO (
very simple 16MHz xtal with varicap arrangement).
All parts in the ordinary spare generic stuff drawer......
Post by Bruce Griffiths
Full wave rectify the sinewave input, extract the 8th Harmonic with a passive filter.
Drive the input of a divide by 5 circuit via a suitable impedance converter network.
Could even use a CMOS 74XX74 flipflop plus a few passive components as the divider.
Bruce
Post by Tom Van Baak
What's a clever, simple, reliable (pick 2 of 3) way to get 16 MHz out of
10 MHz? Low phase noise isn't a big requirement and jitter doesn't need to
be sub-nanosecond. The main requirement is perfect cycle count accuracy.
This is for driving a 16 MHz microcontroller from a 10 MHz Rb/Cs/GPSDO. 10
MHz input is likely sine; 16 MHz output is 3v3 or 5v CMOS.
Post by Tom Van Baak
Thanks,
/tvb
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Francesco Messineo
2018-09-30 07:05:26 UTC
Permalink
Post by Tom Van Baak
What's a clever, simple, reliable (pick 2 of 3) way to get 16 MHz out of 10 MHz? Low phase noise isn't a big requirement and jitter doesn't need to be sub-nanosecond. The main requirement is perfect cycle count accuracy. This is for driving a 16 MHz microcontroller from a 10 MHz Rb/Cs/GPSDO. 10 MHz input is likely sine; 16 MHz output is 3v3 or 5v CMOS.
Thanks,
/tvb
I would square the sine (like HP single BJT or double BJT squarers),
divide by 5 with any 74XX290 or xx390, then multiply by two three
times using 74XX86 XORs with one input delayed by two inverters. You
would need to play with the last inverters delay if your
microcontroller needs a symmetric clock

Frank

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Dana Whitlow
2018-09-30 08:18:33 UTC
Permalink
Tom,

Divide the 10 MHz down to 2 MHz in the usual way, then multiply by 8
with a cascade of three analog freq doublers separated by fairly narrow
bandpass filters. Caveats: Would need four filters total along the path
to get rid of unwanted frequency components, gain distributed along
the path to keep the signal level high enough to satisfy the doublers,
and might suffer excessive phase drift due to temperature changes of
the filters (and probably to a lesser extent) the doublers themselves.
You didn't mention phase stability requirements...

Freq doublers based on mixers or on full-wave rectification have the
pleasant property of having *most* of their output power in the proper
harmonic order, but require sinusoidal drives to work. An unfiltered
digital drive signal won't suffice here.

Dana
Post by Tom Van Baak
What's a clever, simple, reliable (pick 2 of 3) way to get 16 MHz out of
10 MHz? Low phase noise isn't a big requirement and jitter doesn't need to
be sub-nanosecond. The main requirement is perfect cycle count accuracy.
This is for driving a 16 MHz microcontroller from a 10 MHz Rb/Cs/GPSDO. 10
MHz input is likely sine; 16 MHz output is 3v3 or 5v CMOS.
Thanks,
/tvb
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ew via time-nuts
2018-09-30 08:52:09 UTC
Permalink
We use the ICS527 for many applications easy to get 80 or 160 MHz. in non critical applications I use an AC14. Have a small board, 14 and ISC only if interested have to look for it it is pre relocation. Juerg may also have one. Corby uses it in his latest HP5065 tests along with a AD9850 DDS.Bert Kehren
In a message dated 9/30/2018 2:00:05 AM Eastern Standard Time, ***@sfr.fr writes:

How about an ICS525 or ICS527. IDT’s calculator allows a 0 ppm frequency error. You would need a sine-square converter for input.
Post by Tom Van Baak
What's a clever, simple, reliable (pick 2 of 3) way to get 16 MHz out of 10 MHz? Low phase noise isn't a big requirement and jitter doesn't need to be sub-nanosecond. The main requirement is perfect cycle count accuracy. This is for driving a 16 MHz microcontroller from a 10 MHz Rb/Cs/GPSDO. 10 MHz input is likely sine; 16 MHz output is 3v3 or 5v CMOS.
Thanks,
/tvb
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Emma Goldman


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John Ackermann. N8UR
2018-09-30 12:27:58 UTC
Permalink
The clockblock could do that, or probably any of the newer synth chips.  Phase noise and jitter are lousy of course.
Post by Tom Van Baak
What's a clever, simple, reliable (pick 2 of 3) way to get 16 MHz out
of 10 MHz? Low phase noise isn't a big requirement and jitter doesn't
need to be sub-nanosecond. The main requirement is perfect cycle count
accuracy. This is for driving a 16 MHz microcontroller from a 10 MHz
Rb/Cs/GPSDO. 10 MHz input is likely sine; 16 MHz output is 3v3 or 5v
CMOS.
Thanks,
/tvb
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Pete Lancashire
2018-09-30 13:44:41 UTC
Permalink
Same question 10 to 12:-)
Post by Tom Van Baak
What's a clever, simple, reliable (pick 2 of 3) way to get 16 MHz out of
10 MHz? Low phase noise isn't a big requirement and jitter doesn't need to
be sub-nanosecond. The main requirement is perfect cycle count accuracy.
This is for driving a 16 MHz microcontroller from a 10 MHz Rb/Cs/GPSDO. 10
MHz input is likely sine; 16 MHz output is 3v3 or 5v CMOS.
Thanks,
/tvb
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Gerhard Hoffmann
2018-09-30 14:08:10 UTC
Permalink
Post by Pete Lancashire
Same question 10 to 12:-)
Same Answer.

Select pins = (1, 1, 0) for 12 instead of (1, 1, 1) for 16.

\Gerhard



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Mike Feher
2018-09-30 14:26:27 UTC
Permalink
Almost same answer as I gave Tom. Double to 20, divide by 10, and then mix
the 2 with the original 10, You could also just divide by 5 and then mix
that 2 with the original 10. Again, filtering required. 73 - Mike



Mike B. Feher, N4FS

89 Arnold Blvd.

Howell NJ 07731

848-245-9115



-----Original Message-----
From: time-nuts <time-nuts-***@lists.febo.com> On Behalf Of Pete
Lancashire
Sent: Sunday, September 30, 2018 9:45 AM
To: Tom Van Baak <***@leapsecond.com>; Discussion of precise time and
frequency measurement <time-***@lists.febo.com>
Subject: Re: [time-nuts] 10 MHz -> 16 MHz



Same question 10 to 12:-)
Post by Tom Van Baak
What's a clever, simple, reliable (pick 2 of 3) way to get 16 MHz out
of
1Almost 0 MHz? Low phase noise isn't a big requirement and jitter doesn't
need to be sub-nanosecond. The main requirement is perfect cycle count
accuracy.
Post by Tom Van Baak
This is for driving a 16 MHz microcontroller from a 10 MHz
Rb/Cs/GPSDO. 10 MHz input is likely sine; 16 MHz output is 3v3 or 5v CMOS.
Thanks,
/tvb
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Pete Lancashire
2018-09-30 14:30:43 UTC
Permalink
It surprises me how the SDR designers in 90% of the cases don't even allow
for an external clock. It's like accuracy never came into thought.
Post by Tom Van Baak
What's a clever, simple, reliable (pick 2 of 3) way to get 16 MHz out of
10 MHz? Low phase noise isn't a big requirement and jitter doesn't need to
be sub-nanosecond. The main requirement is perfect cycle count accuracy.
This is for driving a 16 MHz microcontroller from a 10 MHz Rb/Cs/GPSDO. 10
MHz input is likely sine; 16 MHz output is 3v3 or 5v CMOS.
Thanks,
/tvb
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Attila Kinali
2018-09-30 14:49:18 UTC
Permalink
On Sat, 29 Sep 2018 20:57:14 -0700
Post by Tom Van Baak
What's a clever, simple, reliable (pick 2 of 3) way to get 16 MHz out of
10 MHz? Low phase noise isn't a big requirement and jitter doesn't need
to be sub-nanosecond. The main requirement is perfect cycle count accuracy.
This is for driving a 16 MHz microcontroller from a 10 MHz Rb/Cs/GPSDO.
10 MHz input is likely sine; 16 MHz output is 3v3 or 5v CMOS.
The simplest way I can think of is the following:
Use a 74LV8154 to divide the 10MHz down to 152.587890625Hz.
Use the capture timer unit of the uC to measure the phase of the
pulse. Use any kind of DAC (internal, external, PWM,...) to steer
the 16MHz VCO. Depending on how fast the timer unit runs, this
will give you something in the order of 10-200ns dead-band.
By choosing the right frequency for the timer unit, one can
get it to "dither" a bit and then use averaging.

For lower jitter, use one half of a Nutt interpolator
to get the timing difference between the 152Hz signal
and the 16MHz (ie similar to what the SRS FS740 does).
Use something akin Nick Sayer's time-to-amplitude converter
for the fine measurement.

Same works equally well for 12MHz.

Attila Kinali
--
<JaberWorky> The bad part of Zurich is where the degenerates
throw DARK chocolate at you.

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Gerhard Hoffmann
2018-09-30 17:05:16 UTC
Permalink
Post by Attila Kinali
Use a 74LV8154 to divide the 10MHz down to 152.587890625Hz.
Use the capture timer unit of the uC to measure the phase of the
pulse. Use any kind of DAC (internal, external, PWM,...) to steer
the 16MHz VCO. Depending on how fast the timer unit runs, this
will give you something in the order of 10-200ns dead-band.
By choosing the right frequency for the timer unit, one can
get it to "dither" a bit and then use averaging.
For lower jitter, use one half of a Nutt interpolator
to get the timing difference between the 152Hz signal
and the 16MHz (ie similar to what the SRS FS740 does).
Use something akin Nick Sayer's time-to-amplitude converter
for the fine measurement.
Same works equally well for 12MHz.
Wow. That's truly a Rube Goldberg design.

There is a simpler way.  IDT ICS570. Digikey 800-1073-5-ND

Solder time less than 10 minutes.
I had the 3V3-Version in the parts drawers, officially it takes the 5V
version to generate the 160 MHz, but the 3V3 version happened to work, too.
The difference between 120 and 160 MHz is just a GND wire on pin 6 (vs.
open)

Divide by 10 is left as an exercise.

regards,
Gerhard

(But then, some like to build and tune multiplier chains and mixers.)
ed breya
2018-09-30 17:32:19 UTC
Permalink
I'd recommend keeping the involved frequencies and power as low as
possible. The VCO/PLL route is probably the most straightforward, but
using arithmetic operations instead can be simpler at this frequency,
because the filtering can be readily done with common crystals.

If you divide the 10 MHz by 5, then mix the resulting 2 MHz back with
the 10, you'll get mostly 12 and 8 MHz. Double that result to get mostly
24 and 16 MHz, then filter the 16 MHz out with as fancy a filter as
necessary. 16 MHz is a very common crystal frequency, so you could do
that for filtering, or even make a ladder filter with a bunch of them.

With the VCO/PLL approach, the desired 16 MHz will be the highest
frequency, while the arithmetic one uses 24 MHz maximum working
frequency, neglecting harmonics. The logic can all be done with 74HC, at
reasonable quietness and power.

Ed

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Attila Kinali
2018-09-30 18:21:33 UTC
Permalink
On Sun, 30 Sep 2018 19:05:16 +0200
Post by Gerhard Hoffmann
Wow. That's truly a Rube Goldberg design.
You are right, one can do it simpler, in a single chip:

Take a uC (STM32F030 comes to mind), use its PLL, VCO and clock output
to do the heavy lifting. No external components (beside a few capacitors)
required.

As the CPU itself and all the peripherals are not used, one can do
other shenanigans with them, like playing the imperial march on
a floppy drive.

Attila Kinali
--
<JaberWorky> The bad part of Zurich is where the degenerates
throw DARK chocolate at you.

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Bob kb8tq
2018-09-30 20:05:32 UTC
Permalink
Hi

If (as originally specified) noise and jitter are not a big deal - there are a lot
of chips out there like the ICS570. They are designed to do weird ratio frequency
conversions so 10 to 12 or 10 to 16 are trivial for them. The Clockblock board was
one way to get it all put together.

Bob
Post by Gerhard Hoffmann
Post by Attila Kinali
Use a 74LV8154 to divide the 10MHz down to 152.587890625Hz.
Use the capture timer unit of the uC to measure the phase of the
pulse. Use any kind of DAC (internal, external, PWM,...) to steer
the 16MHz VCO. Depending on how fast the timer unit runs, this
will give you something in the order of 10-200ns dead-band.
By choosing the right frequency for the timer unit, one can
get it to "dither" a bit and then use averaging.
For lower jitter, use one half of a Nutt interpolator
to get the timing difference between the 152Hz signal
and the 16MHz (ie similar to what the SRS FS740 does).
Use something akin Nick Sayer's time-to-amplitude converter
for the fine measurement.
Same works equally well for 12MHz.
Wow. That's truly a Rube Goldberg design.
There is a simpler way. IDT ICS570. Digikey 800-1073-5-ND
Solder time less than 10 minutes.
I had the 3V3-Version in the parts drawers, officially it takes the 5V
version to generate the 160 MHz, but the 3V3 version happened to work, too.
The difference between 120 and 160 MHz is just a GND wire on pin 6 (vs. open)
Divide by 10 is left as an exercise.
regards,
Gerhard
(But then, some like to build and tune multiplier chains and mixers.)
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Bruce Griffiths
2018-09-30 20:25:57 UTC
Permalink
A low phase noise method is to use a dual conjugate regenerative divider with 6MHz and 16Mhz bandpass filters in the feedback loop to produce 16Mhz output.

For 12MHz output use 2MHz and 12MHz bandpass filters in the feedback loop.

Bruce
Post by Bob kb8tq
Hi
If (as originally specified) noise and jitter are not a big deal - there are a lot
of chips out there like the ICS570. They are designed to do weird ratio frequency
conversions so 10 to 12 or 10 to 16 are trivial for them. The Clockblock board was
one way to get it all put together.
Bob
Post by Gerhard Hoffmann
Post by Attila Kinali
Use a 74LV8154 to divide the 10MHz down to 152.587890625Hz.
Use the capture timer unit of the uC to measure the phase of the
pulse. Use any kind of DAC (internal, external, PWM,...) to steer
the 16MHz VCO. Depending on how fast the timer unit runs, this
will give you something in the order of 10-200ns dead-band.
By choosing the right frequency for the timer unit, one can
get it to "dither" a bit and then use averaging.
For lower jitter, use one half of a Nutt interpolator
to get the timing difference between the 152Hz signal
and the 16MHz (ie similar to what the SRS FS740 does).
Use something akin Nick Sayer's time-to-amplitude converter
for the fine measurement.
Same works equally well for 12MHz.
Wow. That's truly a Rube Goldberg design.
There is a simpler way. IDT ICS570. Digikey 800-1073-5-ND
Solder time less than 10 minutes.
I had the 3V3-Version in the parts drawers, officially it takes the 5V
version to generate the 160 MHz, but the 3V3 version happened to work, too.
The difference between 120 and 160 MHz is just a GND wire on pin 6 (vs. open)
Divide by 10 is left as an exercise.
regards,
Gerhard
(But then, some like to build and tune multiplier chains and mixers.)
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Brian, WA1ZMS
2018-10-03 11:54:07 UTC
Permalink
Bruce-

Does such a dual conjugate regen divider use a single mixer with the BPFs in parallel? Or are there multiple loops? I'm trying to visualize the topology.

I've built a few divide-by-2 regen dividers (both worked very well) but nothing else.

-Brian
Post by Bruce Griffiths
A low phase noise method is to use a dual conjugate regenerative divider with 6MHz and 16Mhz bandpass filters in the feedback loop to produce 16Mhz output.
For 12MHz output use 2MHz and 12MHz bandpass filters in the feedback loop.
Bruce
Post by Bob kb8tq
Hi
If (as originally specified) noise and jitter are not a big deal - there are a lot
of chips out there like the ICS570. They are designed to do weird ratio frequency
conversions so 10 to 12 or 10 to 16 are trivial for them. The Clockblock board was
one way to get it all put together.
Bob
Post by Attila Kinali
Use a 74LV8154 to divide the 10MHz down to 152.587890625Hz.
Use the capture timer unit of the uC to measure the phase of the
pulse. Use any kind of DAC (internal, external, PWM,...) to steer
the 16MHz VCO. Depending on how fast the timer unit runs, this
will give you something in the order of 10-200ns dead-band.
By choosing the right frequency for the timer unit, one can
get it to "dither" a bit and then use averaging.
For lower jitter, use one half of a Nutt interpolator
to get the timing difference between the 152Hz signal
and the 16MHz (ie similar to what the SRS FS740 does).
Use something akin Nick Sayer's time-to-amplitude converter
for the fine measurement.
Same works equally well for 12MHz.
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Magnus Danielson
2018-10-03 13:52:13 UTC
Permalink
Hi Brian,

The typical ones have two amplifier chains in parallel and one mixer.
You take the output from the amplifier branch of your liking.

The hard part is to tune them to run in synchronous mode and ensure they
stay there, or else there is a beat pattern causing excessive jitter
over that of the synchronous mode.

Cheers,
Magnus
Post by Brian, WA1ZMS
Bruce-
Does such a dual conjugate regen divider use a single mixer with the BPFs in parallel? Or are there multiple loops? I'm trying to visualize the topology.
I've built a few divide-by-2 regen dividers (both worked very well) but nothing else.
-Brian
Post by Bruce Griffiths
A low phase noise method is to use a dual conjugate regenerative divider with 6MHz and 16Mhz bandpass filters in the feedback loop to produce 16Mhz output.
For 12MHz output use 2MHz and 12MHz bandpass filters in the feedback loop.
Bruce
Post by Bob kb8tq
Hi
If (as originally specified) noise and jitter are not a big deal - there are a lot
of chips out there like the ICS570. They are designed to do weird ratio frequency
conversions so 10 to 12 or 10 to 16 are trivial for them. The Clockblock board was
one way to get it all put together.
Bob
Post by Attila Kinali
Use a 74LV8154 to divide the 10MHz down to 152.587890625Hz.
Use the capture timer unit of the uC to measure the phase of the
pulse. Use any kind of DAC (internal, external, PWM,...) to steer
the 16MHz VCO. Depending on how fast the timer unit runs, this
will give you something in the order of 10-200ns dead-band.
By choosing the right frequency for the timer unit, one can
get it to "dither" a bit and then use averaging.
For lower jitter, use one half of a Nutt interpolator
to get the timing difference between the 152Hz signal
and the 16MHz (ie similar to what the SRS FS740 does).
Use something akin Nick Sayer's time-to-amplitude converter
for the fine measurement.
Same works equally well for 12MHz.
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Bruce Griffiths
2018-10-03 17:51:03 UTC
Permalink
Brian
There are 2 parallel feedback paths one tuned to 6MHz and the other tuned to 16MHz.
They can either share the same amp or use separate amplifiers. There's a NIST paper on using them to divide by factors other than 2 (e.g. 3, 5 etc).
https://tf.nist.gov/general/pdf/1890.pdf

Bruce
Post by Brian, WA1ZMS
Bruce-
Does such a dual conjugate regen divider use a single mixer with the BPFs in parallel? Or are there multiple loops? I'm trying to visualize the topology.
I've built a few divide-by-2 regen dividers (both worked very well) but nothing else.
-Brian
Post by Bruce Griffiths
A low phase noise method is to use a dual conjugate regenerative divider with 6MHz and 16Mhz bandpass filters in the feedback loop to produce 16Mhz output.
For 12MHz output use 2MHz and 12MHz bandpass filters in the feedback loop.
Bruce
Post by Bob kb8tq
Hi
If (as originally specified) noise and jitter are not a big deal - there are a lot
of chips out there like the ICS570. They are designed to do weird ratio frequency
conversions so 10 to 12 or 10 to 16 are trivial for them. The Clockblock board was
one way to get it all put together.
Bob
Post by Attila Kinali
Use a 74LV8154 to divide the 10MHz down to 152.587890625Hz.
Use the capture timer unit of the uC to measure the phase of the
pulse. Use any kind of DAC (internal, external, PWM,...) to steer
the 16MHz VCO. Depending on how fast the timer unit runs, this
will give you something in the order of 10-200ns dead-band.
By choosing the right frequency for the timer unit, one can
get it to "dither" a bit and then use averaging.
For lower jitter, use one half of a Nutt interpolator
to get the timing difference between the 152Hz signal
and the 16MHz (ie similar to what the SRS FS740 does).
Use something akin Nick Sayer's time-to-amplitude converter
for the fine measurement.
Same works equally well for 12MHz.
_______________________________________________
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Pete Lancashire
2018-10-09 17:25:53 UTC
Permalink
I just wish the tapr would not discontinue things so fast it seems once you
see it mentioned it's discontinued
Post by Bob kb8tq
Hi
If (as originally specified) noise and jitter are not a big deal - there are a lot
of chips out there like the ICS570. They are designed to do weird ratio frequency
conversions so 10 to 12 or 10 to 16 are trivial for them. The Clockblock board was
one way to get it all put together.
Bob
Post by Gerhard Hoffmann
Post by Attila Kinali
Use a 74LV8154 to divide the 10MHz down to 152.587890625Hz.
Use the capture timer unit of the uC to measure the phase of the
pulse. Use any kind of DAC (internal, external, PWM,...) to steer
the 16MHz VCO. Depending on how fast the timer unit runs, this
will give you something in the order of 10-200ns dead-band.
By choosing the right frequency for the timer unit, one can
get it to "dither" a bit and then use averaging.
For lower jitter, use one half of a Nutt interpolator
to get the timing difference between the 152Hz signal
and the 16MHz (ie similar to what the SRS FS740 does).
Use something akin Nick Sayer's time-to-amplitude converter
for the fine measurement.
Same works equally well for 12MHz.
Wow. That's truly a Rube Goldberg design.
There is a simpler way. IDT ICS570. Digikey 800-1073-5-ND
Solder time less than 10 minutes.
I had the 3V3-Version in the parts drawers, officially it takes the 5V
version to generate the 160 MHz, but the 3V3 version happened to work,
too.
Post by Gerhard Hoffmann
The difference between 120 and 160 MHz is just a GND wire on pin 6 (vs.
open)
Post by Gerhard Hoffmann
Divide by 10 is left as an exercise.
regards,
Gerhard
(But then, some like to build and tune multiplier chains and mixers.)
<Auswahl_008.png><times12.bmp><times16.bmp>_______________________________________________
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John Ackermann N8UR
2018-10-09 19:31:36 UTC
Permalink
Hi Pete --

TAPR did one production run of the ClockBlock at the beginning of 2007,
building 100 units, and they were available until all were sold (which
IIRC took a couple of years). I'm not sure if we ever looked at doing a
second run, but I seem to remember that one of the components became
either obsolete or crazy expensive.

But this is a good chance to describe how TAPR handles product
manufacture. We think of ourselves mainly as an R&D organization making
stuff that's not available elsewhere. We're a volunteer, non-profit,
group and the up-front cost to get a bunch of boards assembled is a
major hit to our bank account. We can't afford to build units that will
sit in inventory for years. (This discussion is mainly about assembled
products; the sunk cost for kits is usually much lower.)

So, our usual approach is to do one manufacturing run of a quantity we
are pretty sure will sell out quickly. It's usually not cost-effective
to build less than 50 units, and the per-unit cost drops dramatically as
you increase to 100 or 200 pieces. We do our best to balance unit cost,
upfront cost, and expected sales in a way that's prudent based on our
resources.

We normally don't expect to do a second manufacturing run, as the first
run usually consumes most of the demand. If we place a second order for
a smaller quantity, the unit cost goes up and we would have to increase
price accordingly. If we do a larger order, we risk turning our limited
cash into aging inventory.

There are some cases where the demand justified a second run -- for
example the TICC, where virtually all the units were pre-sold and we
felt comfortable getting a second batch. But our niche market is small
enough that in most cases one run is enough to saturate it.

I believe we have some bare ClockBlock PCBs available; if you're
interested in rolling your own unit, contact me off-line and I'll see
what we can do.

John
----
Post by Pete Lancashire
I just wish the tapr would not discontinue things so fast it seems once you
see it mentioned it's discontinued
Post by Bob kb8tq
Hi
If (as originally specified) noise and jitter are not a big deal - there are a lot
of chips out there like the ICS570. They are designed to do weird ratio frequency
conversions so 10 to 12 or 10 to 16 are trivial for them. The Clockblock board was
one way to get it all put together.
Bob
Post by Gerhard Hoffmann
Post by Attila Kinali
Use a 74LV8154 to divide the 10MHz down to 152.587890625Hz.
Use the capture timer unit of the uC to measure the phase of the
pulse. Use any kind of DAC (internal, external, PWM,...) to steer
the 16MHz VCO. Depending on how fast the timer unit runs, this
will give you something in the order of 10-200ns dead-band.
By choosing the right frequency for the timer unit, one can
get it to "dither" a bit and then use averaging.
For lower jitter, use one half of a Nutt interpolator
to get the timing difference between the 152Hz signal
and the 16MHz (ie similar to what the SRS FS740 does).
Use something akin Nick Sayer's time-to-amplitude converter
for the fine measurement.
Same works equally well for 12MHz.
Wow. That's truly a Rube Goldberg design.
There is a simpler way. IDT ICS570. Digikey 800-1073-5-ND
Solder time less than 10 minutes.
I had the 3V3-Version in the parts drawers, officially it takes the 5V
version to generate the 160 MHz, but the 3V3 version happened to work,
too.
Post by Gerhard Hoffmann
The difference between 120 and 160 MHz is just a GND wire on pin 6 (vs.
open)
Post by Gerhard Hoffmann
Divide by 10 is left as an exercise.
regards,
Gerhard
(But then, some like to build and tune multiplier chains and mixers.)
<Auswahl_008.png><times12.bmp><times16.bmp>_______________________________________________
Post by Gerhard Hoffmann
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Tom Holmes
2018-10-09 19:33:21 UTC
Permalink
Hi Pete...
TAPR doesn't really discontinue things until we've sold out the quantity we've built. Sometimes that is 100pieces, sometimes 500. It all depends on how many we think we can sell when the kit comes out. If we sell out and still see a lot of interest, we may do a second build. The Clock-Block has been around for a few years and took a couple of years to sell out.

From Tom Holmes, N8ZM
Post by Pete Lancashire
I just wish the tapr would not discontinue things so fast it seems once you
see it mentioned it's discontinued
Post by Bob kb8tq
Hi
If (as originally specified) noise and jitter are not a big deal - there are a lot
of chips out there like the ICS570. They are designed to do weird ratio frequency
conversions so 10 to 12 or 10 to 16 are trivial for them. The Clockblock board was
one way to get it all put together.
Bob
Post by Gerhard Hoffmann
Post by Attila Kinali
Use a 74LV8154 to divide the 10MHz down to 152.587890625Hz.
Use the capture timer unit of the uC to measure the phase of the
pulse. Use any kind of DAC (internal, external, PWM,...) to steer
the 16MHz VCO. Depending on how fast the timer unit runs, this
will give you something in the order of 10-200ns dead-band.
By choosing the right frequency for the timer unit, one can
get it to "dither" a bit and then use averaging.
For lower jitter, use one half of a Nutt interpolator
to get the timing difference between the 152Hz signal
and the 16MHz (ie similar to what the SRS FS740 does).
Use something akin Nick Sayer's time-to-amplitude converter
for the fine measurement.
Same works equally well for 12MHz.
Wow. That's truly a Rube Goldberg design.
There is a simpler way. IDT ICS570. Digikey 800-1073-5-ND
Solder time less than 10 minutes.
I had the 3V3-Version in the parts drawers, officially it takes the 5V
version to generate the 160 MHz, but the 3V3 version happened to work,
too.
Post by Gerhard Hoffmann
The difference between 120 and 160 MHz is just a GND wire on pin 6 (vs.
open)
Post by Gerhard Hoffmann
Divide by 10 is left as an exercise.
regards,
Gerhard
(But then, some like to build and tune multiplier chains and mixers.)
<Auswahl_008.png><times12.bmp><times16.bmp>_______________________________________________
Post by Gerhard Hoffmann
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jimlux
2018-09-30 14:54:41 UTC
Permalink
Post by Tom Van Baak
What's a clever, simple, reliable (pick 2 of 3) way to get 16 MHz out of 10 MHz? Low phase noise isn't a big requirement and jitter doesn't need to be sub-nanosecond. The main requirement is perfect cycle count accuracy. This is for driving a 16 MHz microcontroller from a 10 MHz Rb/Cs/GPSDO. 10 MHz input is likely sine; 16 MHz output is 3v3 or 5v CMOS.
Thanks,
/tvb
cycle counts over what interval? 5 and 8 cycles respectively? or over,
say, 1 second?

Multiply by 8 divide by 5 seems a bit tricky (although any number of off
the shelf DDS will do it at fairly high power dissipation)

You might be able to injection lock an 80MHz oscillator by coupling the
10 MHz in on the Vcc or output.

Then a divide by 5 down to 16.

If the requirement is over 1 second, then you can play a game with
counting the first half of the second, and adjusting in the second by
dropping/adding cycles to make it come out right. THat sounds pretty icky.


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Alex Pummer
2018-09-30 17:46:08 UTC
Permalink
and what wold happen if you divide the 10MHz by 10 -- with any simple
counter chip -- and injection lock a 16MHz crystal oscillator with that
1MHz, since the jitter is not critical .... of course it does not hurt
if you make the 1MHz pulses narrow, you could use the micro-controller's
own oscillator circuit, plus that counter [freq divider chip ] it is
simple and cheap enough?

73

KJ6UHN

Alex
Post by Tom Van Baak
What's a clever, simple, reliable (pick 2 of 3) way to get 16 MHz out
of 10 MHz? Low phase noise isn't a big requirement and jitter doesn't
need to be sub-nanosecond. The main requirement is perfect cycle
count accuracy. This is for driving a 16 MHz microcontroller from a
10 MHz Rb/Cs/GPSDO. 10 MHz input is likely sine; 16 MHz output is 3v3
or 5v CMOS.
Thanks,
/tvb
cycle counts over what interval?  5 and 8 cycles respectively? or
over, say,  1 second?
Multiply by 8 divide by 5 seems a bit tricky (although any number of
off the shelf DDS will do it at fairly high power dissipation)
You might be able to injection lock an 80MHz oscillator by coupling
the 10 MHz in on the Vcc or output.
Then a divide by 5 down to 16.
If the requirement is over 1 second, then you can play a game with
counting the first half of the second, and adjusting in the second by
dropping/adding cycles to make it come out right. THat sounds pretty icky.
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ed breya
2018-09-30 18:34:30 UTC
Permalink
I agree with Alex - injection-locking would be the simplest of all, if
the slight correction signal added every 16 cycles is acceptable.

Ed

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Bob Martin
2018-09-30 17:22:29 UTC
Permalink
My 2 cents. Attached image is a little board with OCXO that
outputs 16MHz locked automatically to either 5 or 10MHz. I have
several that will be part of the oscillator giveaway.

I bet someone can figure out how it works from the picture!

Best,

Bob Martin
Post by Tom Van Baak
What's a clever, simple, reliable (pick 2 of 3) way to get 16 MHz out of 10 MHz? Low phase noise isn't a big requirement and jitter doesn't need to be sub-nanosecond. The main requirement is perfect cycle count accuracy. This is for driving a 16 MHz microcontroller from a 10 MHz Rb/Cs/GPSDO. 10 MHz input is likely sine; 16 MHz output is 3v3 or 5v CMOS.
Thanks,
/tvb
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Magnus Danielson
2018-09-30 20:53:43 UTC
Permalink
Hi,

There is clearly enough clock chips today that would fit the bill and
probably provide good enough jitter for you to operate it safely.
Look at products like this:
https://www.silabs.com/products/timing/clocks/general-purpose-clock-generators

There is more of them as you look around.

Then, also consider classic mixer-approach, which may be workable or not
for you:

Square the 10 MHz, feed into a tuned tank for 30 MHz, amplify and
square, divide by 5, mix produced 6 MHz with 10 MHz and amplify into a
tuned tank at 16 MHz, buffer and square as needed for output.

However, for the application at hand I would look at the modern clock
generator chips that has come a long way. Their relatively low noise is
due to their GHz CMOS oscillators and relatively quiet dividers. The
setup gives a relatively good flexibility. Fractional divisors has come
a long way to solve more problems. You get more than the real-estate of
one of the surface mounted DBM mixers would provide you. It's when you
want to go to very low noise that you would consider another approach.

Then again, I would enjoy the challenge of the mixer approach. So choose
method based on what is most rewarding, but for simplicity the clock
chips seems like a good go, so there it is more about locating a cheap
board with the right chip on it.

Cheers,
Magnus
Post by Tom Van Baak
What's a clever, simple, reliable (pick 2 of 3) way to get 16 MHz out of 10 MHz? Low phase noise isn't a big requirement and jitter doesn't need to be sub-nanosecond. The main requirement is perfect cycle count accuracy. This is for driving a 16 MHz microcontroller from a 10 MHz Rb/Cs/GPSDO. 10 MHz input is likely sine; 16 MHz output is 3v3 or 5v CMOS.
Thanks,
/tvb
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Ben Bradley
2018-09-30 19:20:37 UTC
Permalink
There's this clock chip that might do it all-in-one. it has a built-in
PLL and several internal dividers for generating clock signals at a
wide range of frequencies. Adafruit has a breakout board for it.
Unfortunately, some people are calling it a DDS even though it's not:
https://www.mouser.com/new/Silicon-Laboratories/silabssi5351/

How about (my original thought, but the above chip may be perfect for
the job) two doublers to generate 40MHz to drive a DDS set to generate
16MHz? This won't EXACTLY be perfect cycle count as 16/40 (or 2/5)
can't be exactly represented in binary, but I calculate that a 32 bit
approximation would lose 1 cycle about every couple of minutes. The
good part is you can calculate exactly how many cycles off you'll be
based on how long it's been running.
Post by Tom Van Baak
What's a clever, simple, reliable (pick 2 of 3) way to get 16 MHz out of 10 MHz? Low phase noise isn't a big requirement and jitter doesn't need to be sub-nanosecond. The main requirement is perfect cycle count accuracy. This is for driving a 16 MHz microcontroller from a 10 MHz Rb/Cs/GPSDO. 10 MHz input is likely sine; 16 MHz output is 3v3 or 5v CMOS.
Thanks,
/tvb
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Arthur Dent
2018-10-01 00:44:02 UTC
Permalink
Would a divide by 2 followed by a NB3N511 work?
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paul swed
2018-10-01 00:55:37 UTC
Permalink
Arthur that is a very attractive answer. I had never heard of the chip
before surely looks simple enough.
Regards
Paul
WB8TSL
Post by Arthur Dent
Would a divide by 2 followed by a NB3N511 work?
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Arthur Dent
2018-10-01 01:01:31 UTC
Permalink
Oops, I meant divide by 5 to get 2 followed by 8x NB3N511 work?
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Gerhard Hoffmann
2018-10-01 01:35:25 UTC
Permalink
Post by Arthur Dent
Oops, I meant divide by 5 to get 2 followed by 8x NB3N511 work?
_______________________________________________
That should work, also for the 12 MHz case with 6x instead of 8x.

But it still needs a second divider chip like the solution I built
this afternoon. Somewhere, there must exist a single chip SO-8 solution.

:-)

cheers, Gerhard



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Arthur Dent
2018-10-01 01:17:40 UTC
Permalink
I had removed a really crappy 50Mhz SOIC-8 xtal oscillator with no
adjustment and replaced it with a NB3N511 that fit on the same pads (with a
couple small mods). I set it to 5x and fed it with an added internal 10Mhz
OCXO or an external Tbolt and it worked fine. I just made sure to bypass
the power pin to gnd right at the IC.
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Dave B via time-nuts
2018-10-01 15:30:59 UTC
Permalink
Moot point with free running clock oscillators in the digitising sound
cards often used.  Some of the all in one cards with fast A/D's and
FPGA's etc can take an external frequency reference.

Some "adjustment" of the data can be done in software, to calibrate the
frequency domain.  Smoke and mirrors!

But yes, good point.

Dave B.

PS: Thanks to whoever mentioned the ICS525 or 527 IC's.  Oddly, I'd not
come across that family of chips before.  I'm currently messing with an
old-school MC145151 PLL chip, to lock a 20.48MHz VCXO to 10MHz.  I
"abuse" the IC by swapping the reference and VCXO inputs to get the
needed division ratios (for an 80kHz phase comparison frequency.)

That and referencing the tuning diode from the +supply so the loop
tuning is the right way around seems to work scarily well.

The ICS525 would be a better bet perhaps, if I had to manufacture dozens
of the things.  However, making PCB's is an issue for me (no creation
facilities nor experience with the needed layout software) so "dead bug"
construction is the way at the moment!   Fun times...
Post by Pete Lancashire
<<
------------------------------------------------------------------------
Post by Pete Lancashire
It surprises me how the SDR designers in 90% of the cases don't even allow
for an external clock. It's like accuracy never came into thought.
--
Created on and sent from a Unix like PC running and using free and open source software.
::

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a
ew via time-nuts
2018-10-01 16:01:58 UTC
Permalink
I made a mistake in the previous post we use the ICS 570 with very good results in many applications. So it was easy to test. This has to be the easiest and lowest cost circuit. Start with an AC14 ST, followed by a divide by 5. I used part of a HC390 but a LS 90 will do. Take the 2 MHz output feed the input of the 570 and select 16X out comes 32 and 16 MHz. Material cost less than $ 5 regulator included.
Bert Kehren
In a message dated 10/1/2018 11:32:17 AM Eastern Standard Time, time-***@lists.febo.com writes:

Moot point with free running clock oscillators in the digitising soundcards often used.  Some of the all in one cards with fast A/D's andFPGA's etc can take an external frequency reference.
Some "adjustment" of the data can be done in software, to calibrate thefrequency domain.  Smoke and mirrors!
But yes, good point.
Dave B.
PS: Thanks to whoever mentioned the ICS525 or 527 IC's.  Oddly, I'd notcome across that family of chips before.  I'm currently messing with anold-school MC145151 PLL chip, to lock a 20.48MHz VCXO to 10MHz.  I"abuse" the IC by swapping the reference and VCXO inputs to get theneeded division ratios (for an 80kHz phase comparison frequency.)
That and referencing the tuning diode from the +supply so the looptuning is the right way around seems to work scarily well.
The ICS525 would be a better bet perhaps, if I had to manufacture dozensof the things.  However, making PCB's is an issue for me (no creationfacilities nor experience with the needed layout software) so "dead bug"construction is the way at the moment!   Fun times...
<<
------------------------------------------------------------------------On 30/09/18 17:00, time-nuts-***@lists.febo.com wrote:> From: Pete Lancashire <***@petelancashire.com>>>> It surprises me how the SDR designers in 90% of the cases don't even allow> for an external clock. It's like accuracy never came into thought.
-- Created on and sent from a Unix like PC running and using free and open source software.::
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Richard (Rick) Karlquist
2018-10-01 18:24:33 UTC
Permalink
Post by ew via time-nuts
I made a mistake in the previous post we use the ICS 570 with very good results in many applications. So it was easy to test. This has to be the easiest and lowest cost circuit. Start with an AC14 ST, followed by a divide by 5. I used part of a HC390 but a LS 90 will do. Take the 2 MHz output feed the input of the 570 and select 16X out comes 32 and 16 MHz. Material cost less than $ 5 regulator included.
Bert Kehren
The big advantage of the ICS570 vs 99% of the other solutions
is that it does not require a microcontroller to baby sit it.
For a quick and easy solution, that aspect trumps everything
else.

At least for me. I took 1 course in Fortran 50 years ago,
and that was the extent of my software education.
During my whole career, I have too busy being well
paid to design hardware, to have any time left over to
learn software. After Fortran was over, there was the Pascal
fad, then the C fad, etc, now I guess Python is the latest.
Never got involved in any of that.

Rick N6RK

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Bob kb8tq
2018-10-01 19:40:49 UTC
Permalink
Hi

If the device is attaching to a micro controller (as in the original request), feeding it a few
bits to get it set up may not add any parts at all. No, that’s not a certainty, but it usually
is a pretty good guess. Most micro’s these days will start up on an internal clock source so
even the “what to use at time zero” issue is taken care of.

Bob
Post by Richard (Rick) Karlquist
Post by ew via time-nuts
I made a mistake in the previous post we use the ICS 570 with very good results in many applications. So it was easy to test. This has to be the easiest and lowest cost circuit. Start with an AC14 ST, followed by a divide by 5. I used part of a HC390 but a LS 90 will do. Take the 2 MHz output feed the input of the 570 and select 16X out comes 32 and 16 MHz. Material cost less than $ 5 regulator included.
Bert Kehren
The big advantage of the ICS570 vs 99% of the other solutions
is that it does not require a microcontroller to baby sit it.
For a quick and easy solution, that aspect trumps everything
else.
At least for me. I took 1 course in Fortran 50 years ago,
and that was the extent of my software education.
During my whole career, I have too busy being well
paid to design hardware, to have any time left over to
learn software. After Fortran was over, there was the Pascal
fad, then the C fad, etc, now I guess Python is the latest.
Never got involved in any of that.
Rick N6RK
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David G. McGaw
2018-10-02 21:59:51 UTC
Permalink
Another chip to suggest that I have used is the Texas Instruments
CDCE913 (and family).  Wide range of input and output frequencies. If
you have a programmer, it has on-board EEPROM.  Otherwise, it programs
through I2S.

David N1HAC
Post by Bob kb8tq
Hi
If the device is attaching to a micro controller (as in the original request), feeding it a few
bits to get it set up may not add any parts at all. No, that’s not a certainty, but it usually
is a pretty good guess. Most micro’s these days will start up on an internal clock source so
even the “what to use at time zero” issue is taken care of.
Bob
Post by Richard (Rick) Karlquist
Post by ew via time-nuts
I made a mistake in the previous post we use the ICS 570 with very good results in many applications. So it was easy to test. This has to be the easiest and lowest cost circuit. Start with an AC14 ST, followed by a divide by 5. I used part of a HC390 but a LS 90 will do. Take the 2 MHz output feed the input of the 570 and select 16X out comes 32 and 16 MHz. Material cost less than $ 5 regulator included.
Bert Kehren
The big advantage of the ICS570 vs 99% of the other solutions
is that it does not require a microcontroller to baby sit it.
For a quick and easy solution, that aspect trumps everything
else.
At least for me. I took 1 course in Fortran 50 years ago,
and that was the extent of my software education.
During my whole career, I have too busy being well
paid to design hardware, to have any time left over to
learn software. After Fortran was over, there was the Pascal
fad, then the C fad, etc, now I guess Python is the latest.
Never got involved in any of that.
Rick N6RK
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Dan Kemppainen
2018-10-01 16:32:00 UTC
Permalink
The CY2077FZXI might work, if you have a programmer for it...

Dan

Digikey:
https://www.digikey.com/product-detail/en/cypress-semiconductor-corp/CY2077FZXI/CY2077FZXI-ND/2116380
Post by Gerhard Hoffmann
That should work, also for the 12 MHz case with 6x instead of 8x.
But it still needs a second divider chip like the solution I built
this afternoon. Somewhere, there must exist a single chip SO-8 solution.
:-)
cheers, Gerhard
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