Discussion:
HP 5065A A1 replacement with DDS
(too old to reply)
c***@juno.com
2018-06-24 17:21:50 UTC
Permalink
Hi,

I've repaired a few 5065A A1 synthesizer modules recently and lets just
say that they are not my favorite repair!
I decided to go back to a project I started a while back to try and
replace the A1 module with a DDS implementation.
I built up two different styles to evaluate.

One I call the DDS-FE uses a synthesizer board removed from a dead
FE5650A
Rubidium module. It applies the 5Mhz input to a 74HC14 schmitt trigger
which
drives a 570A multiplier giving a 50Mhz output. This is applies to the
synthesizer board (AD9830A) which is configured for the 5.31XXXXMhz
output. This signal is
sent through a one transistor buffer amp with a tuned transformer output.
Frequency is adjusted via RS-232 (pretty much a one time adjustment) and
after
saving is nonvolatile.

The second I call the DDS-BJ. It is a small board that Bert and Juerg
designed
that has schmitt trigger gate and 570 multiplier as well as an 8 pin PIC.
It multiplies the 5Mhz to 100Mhz. The 100Mhz is input to one of the cheap
Chinese
DDS (AD9850) that are available pretty much everywhere. The DDS is
configured
for a 21.24XXXX Mhz square wave output and divided by 4 on the board to
get the 5.31XXXX Mhz output. This is applied via series resonant LC
to the input to the buffer amp. Frequency is adjusted by an up and a down

pushbutton and is nonvolatile. It is cleverly designed to allow the DDS
board to
plug right into the PIC board.

First I installed one into a 5065A that had the super mod installed and
the
performance stayed the same. So that proved DDS was not degrading the
performance.

Then I tried both styles in a standard 5065A that was performing well.
and then plotted the performance. I was a bit surprised that the DDS
units
gave better performance than the original A1!

Either style fits easily inside the original module once the original
circuitry is removed.
Also you could install onto an L shaped aluminum bracket made to fit in
the A1 position.

Attached is a combined plot showing the performance of each and also PIX
of the two DDS styles.

Cheers,

Corby
Poul-Henning Kamp
2018-06-24 17:29:43 UTC
Permalink
--------
Post by c***@juno.com
I've repaired a few 5065A A1 synthesizer modules recently and lets just
say that they are not my favorite repair!
None of my two 5065A's have particular good A1's, so I don't know
what the baseline performance should be like.

I have been playing with this DDS (Hi Bo! :-)

https://www.rudius.net/oz2m/ngnb/dds.htm

And it gives quite an improvement for me.

My plan is to replace the entire chain up to the 60 MHz with that
DDS, and do the modulation digitally, then put one of those
"geophone/optical" 24bit ADC's on the photo-sensor and close the loop.
--
Poul-Henning Kamp | UNIX since Zilog Zeus 3.20
***@FreeBSD.ORG | TCP/IP since RFC 956
FreeBSD committer | BSD since 4.3-tahoe
Never attribute to malice what can adequately be explained by incompetence.
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Attila Kinali
2018-06-24 18:00:22 UTC
Permalink
On Sun, 24 Jun 2018 17:29:43 +0000
Post by Poul-Henning Kamp
My plan is to replace the entire chain up to the 60 MHz with that
DDS, and do the modulation digitally, then put one of those
"geophone/optical" 24bit ADC's on the photo-sensor and close the loop.
I recently thought about that problem and came up with a solution
that might replace more than just A1:

The idea is to use an FPGA (can be a relatively small one) as an I/Q DDS,
then use an I/Q modulator shift the frequency into the right spot
and supressing the mirror. The advantage of using an FPGA instead of
an off the shelf DDS comes from that it makes it possible to connect
an ADC to it, which samples the photo diode voltage and do the demodulation
and integration in the digital domain, thus incuring less noise and zero
drift. Additionally, adding another DAC to generate the 10MHz or any
other frequency directly, gives the possibility to tune the Rb output
in a very wide range without incuring any problems with synthesis chain
and decoupling the reference from the Rb (ie the reference doesn't even
need to be tunable).

Attached is the page of my notebook with the schematic of the idea.
(sorry for the bad handwriting). The components that are not labled
are: PLL: any that can work with the Ref input, e.g. ADF4001.
The VCXO is an ABLJO or any equivalent with 155.52MHz or 156.25MHz.
The divider is a D-FF, either an 74LVC74A or better NB7V52M.
The output frequency of the DDS is in the range of 11-18MHz,
depending on the output frequency and the VCXO frequency.


Attila Kinali
--
It is upon moral qualities that a society is ultimately founded. All
the prosperity and technological sophistication in the world is of no
use without that foundation.
-- Miss Matheson, The Diamond Age, Neil Stephenson
Attila Kinali
2018-06-24 18:06:17 UTC
Permalink
On Sun, 24 Jun 2018 20:00:22 +0200
Post by Attila Kinali
Attached is the page of my notebook with the schematic of the idea.
Oops... I just realized that the mixer part number is wrong.
it should be LTC5599 instead of LTC5598.

Attila Kinali
--
It is upon moral qualities that a society is ultimately founded. All
the prosperity and technological sophistication in the world is of no
use without that foundation.
-- Miss Matheson, The Diamond Age, Neil Stephenson
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Attila Kinali
2018-06-24 18:17:40 UTC
Permalink
On Sun, 24 Jun 2018 20:06:17 +0200
Post by Attila Kinali
Oops... I just realized that the mixer part number is wrong.
it should be LTC5599 instead of LTC5598.
Or not... please ignore me.. I seem to be confused.

Attila Kinalie
--
It is upon moral qualities that a society is ultimately founded. All
the prosperity and technological sophistication in the world is of no
use without that foundation.
-- Miss Matheson, The Diamond Age, Neil Stephenson
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Bruce Griffiths
2018-06-24 21:17:48 UTC
Permalink
In principle DDS spurs due to phase truncation can be largely suppressed using well known techniques when an FPGA is used just leaving spurs due to the DAC.

Bruce
Post by Attila Kinali
On Sun, 24 Jun 2018 17:29:43 +0000
Post by Poul-Henning Kamp
Post by Poul-Henning Kamp
My plan is to replace the entire chain up to the 60 MHz with that
DDS, and do the modulation digitally, then put one of those
"geophone/optical" 24bit ADC's on the photo-sensor and close the loop.
Post by Poul-Henning Kamp
I recently thought about that problem and came up with a solution
The idea is to use an FPGA (can be a relatively small one) as an I/Q DDS,
then use an I/Q modulator shift the frequency into the right spot
and supressing the mirror. The advantage of using an FPGA instead of
an off the shelf DDS comes from that it makes it possible to connect
an ADC to it, which samples the photo diode voltage and do the demodulation
and integration in the digital domain, thus incuring less noise and zero
drift. Additionally, adding another DAC to generate the 10MHz or any
other frequency directly, gives the possibility to tune the Rb output
in a very wide range without incuring any problems with synthesis chain
and decoupling the reference from the Rb (ie the reference doesn't even
need to be tunable).
Attached is the page of my notebook with the schematic of the idea.
(sorry for the bad handwriting). The components that are not labled
are: PLL: any that can work with the Ref input, e.g. ADF4001.
The VCXO is an ABLJO or any equivalent with 155.52MHz or 156.25MHz.
The divider is a D-FF, either an 74LVC74A or better NB7V52M.
The output frequency of the DDS is in the range of 11-18MHz,
depending on the output frequency and the VCXO frequency.
Attila Kinali
--
It is upon moral qualities that a society is ultimately founded. All
the prosperity and technological sophistication in the world is of no
use without that foundation.
-- Miss Matheson, The Diamond Age, Neil Stephenson
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Poul-Henning Kamp
2018-06-24 22:22:47 UTC
Permalink
--------
Post by Bruce Griffiths
In principle DDS spurs due to phase truncation can be largely suppressed using well known techniques when an FPGA is used just leaving spurs due to the DAC.
If (as I plan) the DDS is used to create the LF modulation, then
the spurs are unlikely to matter anyway, as they are not going to
be stationary.
--
Poul-Henning Kamp | UNIX since Zilog Zeus 3.20
***@FreeBSD.ORG | TCP/IP since RFC 956
FreeBSD committer | BSD since 4.3-tahoe
Never attribute to malice what can adequately be explained by incompetence.
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Bob kb8tq
2018-06-24 18:22:14 UTC
Permalink
Hi

One of the things I’ve run into doing Rb’s this way is that the spurs out of the DDS
are not always the same device to device. They also change a lot with small tuning
changes. The result can be a very close in spur ( like << 1 Hz) that really rips up
your ADEV since it passes through all the cleanup PLL’s …. It’s a rare occurrence,
but it does actually happen.

Bob
Post by c***@juno.com
Hi,
I've repaired a few 5065A A1 synthesizer modules recently and lets just
say that they are not my favorite repair!
I decided to go back to a project I started a while back to try and
replace the A1 module with a DDS implementation.
I built up two different styles to evaluate.
One I call the DDS-FE uses a synthesizer board removed from a dead
FE5650A
Rubidium module. It applies the 5Mhz input to a 74HC14 schmitt trigger
which
drives a 570A multiplier giving a 50Mhz output. This is applies to the
synthesizer board (AD9830A) which is configured for the 5.31XXXXMhz
output. This signal is
sent through a one transistor buffer amp with a tuned transformer output.
Frequency is adjusted via RS-232 (pretty much a one time adjustment) and
after
saving is nonvolatile.
The second I call the DDS-BJ. It is a small board that Bert and Juerg
designed
that has schmitt trigger gate and 570 multiplier as well as an 8 pin PIC.
It multiplies the 5Mhz to 100Mhz. The 100Mhz is input to one of the cheap
Chinese
DDS (AD9850) that are available pretty much everywhere. The DDS is
configured
for a 21.24XXXX Mhz square wave output and divided by 4 on the board to
get the 5.31XXXX Mhz output. This is applied via series resonant LC
to the input to the buffer amp. Frequency is adjusted by an up and a down
pushbutton and is nonvolatile. It is cleverly designed to allow the DDS
board to
plug right into the PIC board.
First I installed one into a 5065A that had the super mod installed and
the
performance stayed the same. So that proved DDS was not degrading the
performance.
Then I tried both styles in a standard 5065A that was performing well.
and then plotted the performance. I was a bit surprised that the DDS
units
gave better performance than the original A1!
Either style fits easily inside the original module once the original
circuitry is removed.
Also you could install onto an L shaped aluminum bracket made to fit in
the A1 position.
Attached is a combined plot showing the performance of each and also PIX
of the two DDS styles.
Cheers,
Corby<ORIGINALvsDDSA1.pngi.jpg><ddsbjpix.jpg><feddsrs.jpg>_______________________________________________
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Poul-Henning Kamp
2018-06-24 18:38:13 UTC
Permalink
--------
Post by Bob kb8tq
The result can be a very close in spur ( like << 1 Hz) that really rips up
your ADEV since it passes through all the cleanup PLL’s ….
Indeed.

That's one of the reason I went with Bo's DDS (32bit0 instead of
the eBay modules (20-24 bit). Higher resolution mitigates the spur
problem at least a little bit.
--
Poul-Henning Kamp | UNIX since Zilog Zeus 3.20
***@FreeBSD.ORG | TCP/IP since RFC 956
FreeBSD committer | BSD since 4.3-tahoe
Never attribute to malice what can adequately be explained by incompetence.
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Attila Kinali
2018-06-24 21:34:35 UTC
Permalink
On Sun, 24 Jun 2018 14:05:52 -0700
Does anybody have a handy formula for the spurs given the parameters for a DDS?
I think, you are looking for [1] and [2].

But please note, that both phase truncation and DAC non-linearity
spurs can be reduced by the right use of delta-sigma modulators,
which neither of the papers take into account (for obvious reasons).
For that, I suggest having a look at [3].

Attila Kinali


[1] "How to Predict the Frequency and Magnitude of the Primary Phase
Truncation Spur in the Output Spectrum of a Direct Digital Synthesizer (DDS)",
AN-1396, 2016, by Ken Gentile, Analog Devices
http://www.analog.com/media/en/technical-documentation/application-notes/AN-1396.pdf

[2] "Exact Analysis of DDS Spurs and SNR due to Phase Truncation and
Arbitrary Phase-to-Amplitude Errors", 2005, by Torosyan, Wilson,
http://tycho.usno.navy.mil/ptti/2005papers/paper8.pdf

[3] "Understanding Delta-Sigma Data Converters", 2017, by Pavan, Schreier, Temes
http://onlinelibrary.wiley.com/book/10.1002/9781119258308
--
It is upon moral qualities that a society is ultimately founded. All
the prosperity and technological sophistication in the world is of no
use without that foundation.
-- Miss Matheson, The Diamond Age, Neil Stephenson
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Attila Kinali
2018-06-24 18:57:57 UTC
Permalink
On Sun, 24 Jun 2018 14:22:14 -0400
Post by Bob kb8tq
One of the things I’ve run into doing Rb’s this way is that the spurs out of the DDS
are not always the same device to device. They also change a lot with small tuning
changes. The result can be a very close in spur ( like << 1 Hz) that really rips up
your ADEV since it passes through all the cleanup PLL’s …. It’s a rare occurrence,
but it does actually happen.
With DDS in FPGA you can work around these issues. E.g. the phase
accumulator can be arbitrary wide with moderate cost (48bit would
be in the order of 3k-8kLE) and you can employ additional techniques
to minimize spurs due to the non-linearity of the DAC.


Attila Kinali
--
It is upon moral qualities that a society is ultimately founded. All
the prosperity and technological sophistication in the world is of no
use without that foundation.
-- Miss Matheson, The Diamond Age, Neil Stephenson
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Bob kb8tq
2018-06-24 19:51:24 UTC
Permalink
Hi

Half of the problem is on the digital side. The other half is on the DAC
side of things. More bits / wider registers is fine for the digital stuff. Once
you narrow the bit range down to feed a rational DAC problems begin
to creep in. Now shove that into a DAC that does not have *perfect* linearity
and even more problems crop up.

Bob
Post by Attila Kinali
On Sun, 24 Jun 2018 14:22:14 -0400
Post by Bob kb8tq
One of the things I’ve run into doing Rb’s this way is that the spurs out of the DDS
are not always the same device to device. They also change a lot with small tuning
changes. The result can be a very close in spur ( like << 1 Hz) that really rips up
your ADEV since it passes through all the cleanup PLL’s …. It’s a rare occurrence,
but it does actually happen.
With DDS in FPGA you can work around these issues. E.g. the phase
accumulator can be arbitrary wide with moderate cost (48bit would
be in the order of 3k-8kLE) and you can employ additional techniques
to minimize spurs due to the non-linearity of the DAC.
Attila Kinali
--
It is upon moral qualities that a society is ultimately founded. All
the prosperity and technological sophistication in the world is of no
use without that foundation.
-- Miss Matheson, The Diamond Age, Neil Stephenson
_______________________________________________
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Richard (Rick) Karlquist
2018-06-25 16:30:31 UTC
Permalink
Post by c***@juno.com
Hi,
I've repaired a few 5065A A1 synthesizer modules recently and lets just
say that they are not my favorite repair!
I decided to go back to a project I started a while back to try and
replace the A1 module with a DDS implementation.
I built up two different styles to evaluate.
The original 5065 used an M/N synthesizer. It seems to be stated
(as if it is obvious) that a DDS either has (1) better performance
or (2) is easier/cheaper, etc than an M/N. It is very simple and cheap
to make an M/N loop using synthesizer-on-a-chip IC's from ADI,
TI, etc. You should be able to clone the M and N numbers which
represent a proven design.

DDS's are much riskier as others have pointed out. For the
5071A we used a DDS to make an offset frequency. But there
are some qualifications:

1. It was only for offset, not in the main multiplier chain.

2. It locked a VCXO, so only close in spurs of the DDS mattered.

3. It didn't use COTS DDC chips but was custom built using
74ACXXX logic (SOTA 30 years ago) by Robin Giffard (an
extremely talented engineer) and had a special "blanking
circuit", as Robin called it, that cleaned up the DAC.

Did I miss the reason as to what was wrong with M/N?

Rick N6RK
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Poul-Henning Kamp
2018-06-25 17:47:07 UTC
Permalink
--------
Post by Richard (Rick) Karlquist
Did I miss the reason as to what was wrong with M/N?
I don't think there is anything wrong with M/N, but the A1 in
HP5065 suffers from dead/drifting/dying and obsolete components
in the divider.

I tried replacing the divider with a microcontroller, and that
seemed to work, but as I mentioned, my end-plans are slightly
more ambitious.
--
Poul-Henning Kamp | UNIX since Zilog Zeus 3.20
***@FreeBSD.ORG | TCP/IP since RFC 956
FreeBSD committer | BSD since 4.3-tahoe
Never attribute to malice what can adequately be explained by incompetence.
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ew via time-nuts
2018-06-25 18:46:49 UTC
Permalink
Doesn't the 5062 use M/N
Bert Kehren
 
In a message dated 6/25/2018 12:31:10 PM Eastern Standard Time, ***@karlquist.com writes:

 
Post by c***@juno.com
Hi,
I've repaired a few 5065A A1 synthesizer modules recently and lets just
say that they are not my favorite repair!
I decided to go back to a project I started a while back to try and
replace the A1 module with a DDS implementation.
I built up two different styles to evaluate.
The original 5065 used an M/N synthesizer. It seems to be stated
(as if it is obvious) that a DDS either has (1) better performance
or (2) is easier/cheaper, etc than an M/N. It is very simple and cheap
to make an M/N loop using synthesizer-on-a-chip IC's from ADI,
TI, etc. You should be able to clone the M and N numbers which
represent a proven design.

DDS's are much riskier as others have pointed out. For the
5071A we used a DDS to make an offset frequency. But there
are some qualifications:

1. It was only for offset, not in the main multiplier chain.

2. It locked a VCXO, so only close in spurs of the DDS mattered.

3. It didn't use COTS DDC chips but was custom built using
74ACXXX logic (SOTA 30 years ago) by Robin Giffard (an
extremely talented engineer) and had a special "blanking
circuit", as Robin called it, that cleaned up the DAC.

Did I miss the reason as to what was wrong with M/N?

Rick N6RK
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c***@juno.com
2018-06-25 20:13:54 UTC
Permalink
Bert,

Yes the 5062C also used the same synthesizer style as the 5065A and
5061A/B.

Cheers,

Corby

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