Discussion:
Programmable clock for BFO use....noise
(too old to reply)
l***@cox.net
2018-09-14 16:14:44 UTC
Permalink
Off topic for this list, but you guys are experts in oscillator noise!

Playing with some mechanical filters. Need USB and LSB crystals for the BFO. No one seems to make crystals anymore, especially in the 253 KHz range!

Looking at the DigiKey Cardinal programmable oscillators. Cheap and available: CPPC1LZ A5B6

Anyone have an idea how noisy these would be after a division by 4 to get them in range?

Thanks,

N0UU
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paul swed
2018-09-14 19:05:09 UTC
Permalink
Not sure it would be the noise divided by 4. Not a useful answer.
I looked at those types of units. I thought they were factory programmed.
I may be wrong but was not of the opinion they were single unit buys.
Regards
WB8TSL

On Fri, Sep 14, 2018 at 12:14 PM, <***@cox.net> wrote:

> Off topic for this list, but you guys are experts in oscillator noise!
>
> Playing with some mechanical filters. Need USB and LSB crystals for the
> BFO. No one seems to make crystals anymore, especially in the 253 KHz
> range!
>
> Looking at the DigiKey Cardinal programmable oscillators. Cheap and
> available: CPPC1LZ A5B6
>
> Anyone have an idea how noisy these would be after a division by 4 to get
> them in range?
>
> Thanks,
>
> N0UU
> _______________________________________________
> time-nuts mailing list -- time-***@lists.febo.com
> To unsubscribe, go to http://lists.febo.com/mailman/
> listinfo/time-nuts_lists.febo.com
> and follow the instructions there.
>
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Wes
2018-09-14 19:19:26 UTC
Permalink
I'd look for the appropriate crystals. If it will help, I have a 250.00 kHz one
you can have.

Wes  N7WS

On 9/14/2018 9:14 AM, ***@cox.net wrote:
> Off topic for this list, but you guys are experts in oscillator noise!
>
> Playing with some mechanical filters. Need USB and LSB crystals for the BFO. No one seems to make crystals anymore, especially in the 253 KHz range!
>
> Looking at the DigiKey Cardinal programmable oscillators. Cheap and available: CPPC1LZ A5B6
>
> Anyone have an idea how noisy these would be after a division by 4 to get them in range?
>
> Thanks,
>
> N0UU
> _______________________________________________
> time-nuts mailing list -- time-***@lists.febo.com
> To unsubscribe, go to http://lists.febo.com/mailman/listinfo/time-nuts_lists.febo.com
> and follow the instructions there.
>


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Dana Whitlow
2018-09-14 19:55:01 UTC
Permalink
Frequency dividers can be pretty low noise, if you choose the right class
of logic. I remember that
at one time in the distant past, LSTTL was considered king. Unfortunately
I've been out of touch
with frequency dividers long enough to be ignorant of what works well today.

i'd suggest trying something with either HC-series or AC-series CMOS,
chances are fair that you'd
be happy. Write me off list and I'll tell you which well-known distributor
still has an excellent
selection of HC and AC parts in stock.

Dana


On Fri, Sep 14, 2018 at 11:14 AM, <***@cox.net> wrote:

> Off topic for this list, but you guys are experts in oscillator noise!
>
> Playing with some mechanical filters. Need USB and LSB crystals for the
> BFO. No one seems to make crystals anymore, especially in the 253 KHz
> range!
>
> Looking at the DigiKey Cardinal programmable oscillators. Cheap and
> available: CPPC1LZ A5B6
>
> Anyone have an idea how noisy these would be after a division by 4 to get
> them in range?
>
> Thanks,
>
> N0UU
> _______________________________________________
> time-nuts mailing list -- time-***@lists.febo.com
> To unsubscribe, go to http://lists.febo.com/mailman/
> listinfo/time-nuts_lists.febo.com
> and follow the instructions there.
>
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Richard (Rick) Karlquist
2018-09-14 20:26:32 UTC
Permalink
The AC series is really quite good on phase noise; I used it in
the 5071A at 80 MHz.

Rick N6RK

On 9/14/2018 12:55 PM, Dana Whitlow wrote:
> Frequency dividers can be pretty low noise, if you choose the right class
> of logic. I remember that
> at one time in the distant past, LSTTL was considered king. Unfortunately
> I've been out of touch
> with frequency dividers long enough to be ignorant of what works well today.
>
> i'd suggest trying something with either HC-series or AC-series CMOS,

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paul swed
2018-09-14 21:32:36 UTC
Permalink
As a suggestion I collaborate with a Canadian ham some 5 years ago using a
DDS as a BFO for the HP 3586. Those details were shared on time-nuts if
they are still in the archives.That worked really well. I recall he was a
VE3??? The 3586 had 2 crystals for the BFO while the entire rest of the
system was locked to a single reference. Adding the DDS really reduced the
BFO behaviors that we typical hams wouldn't really notice. It also sound
very clean.
Regards
Paul
WB8TSL

On Fri, Sep 14, 2018 at 4:26 PM, Richard (Rick) Karlquist <
***@karlquist.com> wrote:

> The AC series is really quite good on phase noise; I used it in
> the 5071A at 80 MHz.
>
> Rick N6RK
>
> On 9/14/2018 12:55 PM, Dana Whitlow wrote:
>
>> Frequency dividers can be pretty low noise, if you choose the right class
>> of logic. I remember that
>> at one time in the distant past, LSTTL was considered king. Unfortunately
>> I've been out of touch
>> with frequency dividers long enough to be ignorant of what works well
>> today.
>>
>> i'd suggest trying something with either HC-series or AC-series CMOS,
>>
>
> _______________________________________________
> time-nuts mailing list -- time-***@lists.febo.com
> To unsubscribe, go to http://lists.febo.com/mailman/
> listinfo/time-nuts_lists.febo.com
> and follow the instructions there.
>
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Bryan _
2018-09-14 21:42:05 UTC
Permalink
I would be interested in hearing more of the more suitable classes of logic chips. I have a 20Mhz rubidium that I wanted to divide down to 10Mhz

-=Bryan=-

________________________________
From: time-nuts <time-nuts-***@lists.febo.com> on behalf of Dana Whitlow <***@gmail.com>
Sent: September 14, 2018 12:55 PM
To: ***@cox.net; Discussion of precise time and frequency measurement
Subject: Re: [time-nuts] Programmable clock for BFO use....noise

Frequency dividers can be pretty low noise, if you choose the right class
of logic. I remember that
at one time in the distant past, LSTTL was considered king. Unfortunately
I've been out of touch
with frequency dividers long enough to be ignorant of what works well today.

i'd suggest trying something with either HC-series or AC-series CMOS,
chances are fair that you'd
be happy. Write me off list and I'll tell you which well-known distributor
still has an excellent
selection of HC and AC parts in stock.

Dana


On Fri, Sep 14, 2018 at 11:14 AM, <***@cox.net> wrote:

> Off topic for this list, but you guys are experts in oscillator noise!
>
> Playing with some mechanical filters. Need USB and LSB crystals for the
> BFO. No one seems to make crystals anymore, especially in the 253 KHz
> range!
>
> Looking at the DigiKey Cardinal programmable oscillators. Cheap and
> available: CPPC1LZ A5B6
>
> Anyone have an idea how noisy these would be after a division by 4 to get
> them in range?
>
> Thanks,
>
> N0UU
> _______________________________________________
> time-nuts mailing list -- time-***@lists.febo.com
> To unsubscribe, go to http://lists.febo.com/mailman/
> listinfo/time-nuts_lists.febo.com
> and follow the instructions there.
>
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Attila Kinali
2018-09-15 10:26:33 UTC
Permalink
On Fri, 14 Sep 2018 21:42:05 +0000
Bryan _ <***@outlook.com> wrote:

> I would be interested in hearing more of the more suitable classes of
> logic chips. I have a 20Mhz rubidium that I wanted to divide down to 10Mhz

Any logic family works, as long as it is fast enough to handle your
input frequency. Due to the non-linear (aka digital) behaviour
of a D-Flipflop style divider, it is recommended to use the slowest
possible logic family for the task. Otherwise the harmonics of the
switching of the FF will down-mix high frequency white noise down
to the signal band (this is the reason for the 10*log(N) noise scaling
of digital divider that Egan[1] and Calosso/Rubiola[2] and a few others
mentioned).

As a rule of thumb, I'd say that the FF should not be more than 10 to 20
times faster than the input frequency, to limit noise down-mixing.
If your FF is too fast or you want to reduce the noise floor, capacitively
loading and/or having some additional resistance in the Vcc and GND lines
will help slow it down. But ensure that the resistance is still low enough
that the FF's supply stays within specs at all time. Similarly, the
capacitive loading should be low enough that the output current is within
reasonable bounds.

Alternatively, using the Λ-divider approach[2] and introducing voltage
steps between 0 and 1 will also reduce down-mixing.

If you divide by something that is not a power of 2, then it is important
that each stage produces an output waveform with a 50% duty cycle. Otherwise
flicker noise which has been up-mixed by a previous stage, will be down-mixed
into the signal band, increasing the close-in phase-noise.


Attila Kinali

[1] "Modeling Phase Noise in Frequency Dividers," by Egan, 1990

[2] "The Sampling Theorem in Pi and Lambda Digital Frequency Dividers,"
by Calosso and Rubiola 2013

--
<JaberWorky> The bad part of Zurich is where the degenerates
throw DARK chocolate at you.

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Dr. Ulrich L. Rohde via time-nuts
2018-09-15 10:33:55 UTC
Permalink
Good points, Ulrich Rohde

Sent from my iPhone

> On Sep 15, 2018, at 6:26 AM, Attila Kinali <***@kinali.ch> wrote:
>
> On Fri, 14 Sep 2018 21:42:05 +0000
> Bryan _ <***@outlook.com> wrote:
>
>> I would be interested in hearing more of the more suitable classes of
>> logic chips. I have a 20Mhz rubidium that I wanted to divide down to 10Mhz
>
> Any logic family works, as long as it is fast enough to handle your
> input frequency. Due to the non-linear (aka digital) behaviour
> of a D-Flipflop style divider, it is recommended to use the slowest
> possible logic family for the task. Otherwise the harmonics of the
> switching of the FF will down-mix high frequency white noise down
> to the signal band (this is the reason for the 10*log(N) noise scaling
> of digital divider that Egan[1] and Calosso/Rubiola[2] and a few others
> mentioned).
>
> As a rule of thumb, I'd say that the FF should not be more than 10 to 20
> times faster than the input frequency, to limit noise down-mixing.
> If your FF is too fast or you want to reduce the noise floor, capacitively
> loading and/or having some additional resistance in the Vcc and GND lines
> will help slow it down. But ensure that the resistance is still low enough
> that the FF's supply stays within specs at all time. Similarly, the
> capacitive loading should be low enough that the output current is within
> reasonable bounds.
>
> Alternatively, using the Λ-divider approach[2] and introducing voltage
> steps between 0 and 1 will also reduce down-mixing.
>
> If you divide by something that is not a power of 2, then it is important
> that each stage produces an output waveform with a 50% duty cycle. Otherwise
> flicker noise which has been up-mixed by a previous stage, will be down-mixed
> into the signal band, increasing the close-in phase-noise.
>
>
> Attila Kinali
>
> [1] "Modeling Phase Noise in Frequency Dividers," by Egan, 1990
>
> [2] "The Sampling Theorem in Pi and Lambda Digital Frequency Dividers,"
> by Calosso and Rubiola 2013
>
> --
> <JaberWorky> The bad part of Zurich is where the degenerates
> throw DARK chocolate at you.
>
> _______________________________________________
> time-nuts mailing list -- time-***@lists.febo.com
> To unsubscribe, go to http://lists.febo.com/mailman/listinfo/time-nuts_lists.febo.com
> and follow the instructions there.


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Club-Internet Clemgill
2018-09-15 11:13:40 UTC
Permalink
Hi Attila,
Very interesting, thanks.
I found ref (2) by seems that need to pay or be to registered as a researcher to get ref (1).
Is there a easier way to get a copy ?
Thx,
Gilles.

> Le 15 sept. 2018 à 12:26, Attila Kinali <***@kinali.ch> a écrit :
>
> On Fri, 14 Sep 2018 21:42:05 +0000
> Bryan _ <***@outlook.com> wrote:
>
>> I would be interested in hearing more of the more suitable classes of
>> logic chips. I have a 20Mhz rubidium that I wanted to divide down to 10Mhz
>
> Any logic family works, as long as it is fast enough to handle your
> input frequency. Due to the non-linear (aka digital) behaviour
> of a D-Flipflop style divider, it is recommended to use the slowest
> possible logic family for the task. Otherwise the harmonics of the
> switching of the FF will down-mix high frequency white noise down
> to the signal band (this is the reason for the 10*log(N) noise scaling
> of digital divider that Egan[1] and Calosso/Rubiola[2] and a few others
> mentioned).
>
> As a rule of thumb, I'd say that the FF should not be more than 10 to 20
> times faster than the input frequency, to limit noise down-mixing.
> If your FF is too fast or you want to reduce the noise floor, capacitively
> loading and/or having some additional resistance in the Vcc and GND lines
> will help slow it down. But ensure that the resistance is still low enough
> that the FF's supply stays within specs at all time. Similarly, the
> capacitive loading should be low enough that the output current is within
> reasonable bounds.
>
> Alternatively, using the Λ-divider approach[2] and introducing voltage
> steps between 0 and 1 will also reduce down-mixing.
>
> If you divide by something that is not a power of 2, then it is important
> that each stage produces an output waveform with a 50% duty cycle. Otherwise
> flicker noise which has been up-mixed by a previous stage, will be down-mixed
> into the signal band, increasing the close-in phase-noise.
>
>
> Attila Kinali
>
> [1] "Modeling Phase Noise in Frequency Dividers," by Egan, 1990
>
> [2] "The Sampling Theorem in Pi and Lambda Digital Frequency Dividers,"
> by Calosso and Rubiola 2013
>
> --
> <JaberWorky> The bad part of Zurich is where the degenerates
> throw DARK chocolate at you.
>
> _______________________________________________
> time-nuts mailing list -- time-***@lists.febo.com
> To unsubscribe, go to http://lists.febo.com/mailman/listinfo/time-nuts_lists.febo.com
> and follow the instructions there.


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Attila Kinali
2018-09-15 12:29:08 UTC
Permalink
On Sat, 15 Sep 2018 13:13:40 +0200
Club-Internet Clemgill <***@club-internet.fr> wrote:

> Very interesting, thanks.
> I found ref (2) by seems that need to pay or be to registered as a researcher to get ref (1).
> Is there a easier way to get a copy ?

Yes, use sci-hub: https://sci-hub.tw/10.1109/58.56498

Attila Kinali

--
<JaberWorky> The bad part of Zurich is where the degenerates
throw DARK chocolate at you.

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Richard (Rick) Karlquist
2018-09-15 15:38:55 UTC
Permalink
Another great posting from Attila that keeps the S/N ratio
on this list high.

On 9/15/2018 3:26 AM, Attila Kinali wrote:

> possible logic family for the task. Otherwise the harmonics of the
> switching of the FF will down-mix high frequency white noise down
> to the signal band (this is the reason for the 10*log(N) noise scaling
> of digital divider that Egan[1] and Calosso/Rubiola[2] and a few others
> mentioned).

Wow, I never knew this in 45 years of designing synthesizers!
I do remember that some of the frequency counter engineers at HP
talked about noise aliasing. I think this is another way of
describing the same problem.

About 10 years ago, the frequency synthesizer chip vendors started
talking about a Figure of Merit (FOM) that predicted phase noise floor,
and it also included the 10 LOG N noise scaling. An application
engineer at ADI told me this was a characteristic of the sampling phase
detector that all these chips used. But I always wondered if the
frequency divider could come into play. The way FOM is defined,
it doesn't distinguish between phase detector and divider noise.

At Agilent, we used to make a lot of lab demos using a Centellax
(now Microsemi AKA Microchip) frequency divider that could divide by any
number between 8 and 511 up to 10 GHz. It was absolutely fabulous for
dividing 10 GHz down to 2.5 GHz. But 20 LOG N quit working if I tried
to divide down to 50 MHz. Now you have explained it.
>
> If you divide by something that is not a power of 2, then it is important
> that each stage produces an output waveform with a 50% duty cycle. Otherwise
> flicker noise which has been up-mixed by a previous stage, will be down-mixed
> into the signal band, increasing the close-in phase-noise.

Wow, another thing I never knew. The conventional wisdom was to
divide by any number (even or odd) and then follow that divider
with a divide by 2 flip flop to get 50%. Now, that is in question.
The now correct answer is to us a variable modulus prescaler to
divide by P and P+1, controlled by a toggle flip flop to make
half the divisions at P and half at P+1.

Does anyone else have experience with these issues?

Rick N6RK


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Scott Stobbe
2018-09-16 02:05:12 UTC
Permalink
That is fascinating. So, the 1PPS line on a GPSDO (a divide by 10Meg in
many cases) is 70 dB worse than the traditional 20log(N) PN scaling?

On Sat, Sep 15, 2018 at 11:40 AM Richard (Rick) Karlquist <
***@karlquist.com> wrote:

> Another great posting from Attila that keeps the S/N ratio
> on this list high.
>
> On 9/15/2018 3:26 AM, Attila Kinali wrote:
>
> > possible logic family for the task. Otherwise the harmonics of the
> > switching of the FF will down-mix high frequency white noise down
> > to the signal band (this is the reason for the 10*log(N) noise scaling
> > of digital divider that Egan[1] and Calosso/Rubiola[2] and a few others
> > mentioned).
>
> Wow, I never knew this in 45 years of designing synthesizers!
> I do remember that some of the frequency counter engineers at HP
> talked about noise aliasing. I think this is another way of
> describing the same problem.
>
> About 10 years ago, the frequency synthesizer chip vendors started
> talking about a Figure of Merit (FOM) that predicted phase noise floor,
> and it also included the 10 LOG N noise scaling. An application
> engineer at ADI told me this was a characteristic of the sampling phase
> detector that all these chips used. But I always wondered if the
> frequency divider could come into play. The way FOM is defined,
> it doesn't distinguish between phase detector and divider noise.
>
> At Agilent, we used to make a lot of lab demos using a Centellax
> (now Microsemi AKA Microchip) frequency divider that could divide by any
> number between 8 and 511 up to 10 GHz. It was absolutely fabulous for
> dividing 10 GHz down to 2.5 GHz. But 20 LOG N quit working if I tried
> to divide down to 50 MHz. Now you have explained it.
> >
> > If you divide by something that is not a power of 2, then it is important
> > that each stage produces an output waveform with a 50% duty cycle.
> Otherwise
> > flicker noise which has been up-mixed by a previous stage, will be
> down-mixed
> > into the signal band, increasing the close-in phase-noise.
>
> Wow, another thing I never knew. The conventional wisdom was to
> divide by any number (even or odd) and then follow that divider
> with a divide by 2 flip flop to get 50%. Now, that is in question.
> The now correct answer is to us a variable modulus prescaler to
> divide by P and P+1, controlled by a toggle flip flop to make
> half the divisions at P and half at P+1.
>
> Does anyone else have experience with these issues?
>
> Rick N6RK
>
>
> _______________________________________________
> time-nuts mailing list -- time-***@lists.febo.com
> To unsubscribe, go to
> http://lists.febo.com/mailman/listinfo/time-nuts_lists.febo.com
> and follow the instructions there.
>
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Bob kb8tq
2018-09-16 02:57:31 UTC
Permalink
Hi

Most of the traditional rules about phase noise apply out to 10 or 20% of the “carrier”
frequency. If the carrier is 1Hz, then you are talking about the traditional definitions holding
out to 0.1 or 0.2 Hz relative to carrier. That’s *deep* in the 1/F noise part of the divider’s
“noise curve”.

Since the ADEV of the 1 PPS is typically no worse than the ADEV of the 10 MHz, it would be
hard to come up with a model where the 1 PPS has picked up a lot of extra noise.

Bob

> On Sep 15, 2018, at 9:05 PM, Scott Stobbe <***@gmail.com> wrote:
>
> That is fascinating. So, the 1PPS line on a GPSDO (a divide by 10Meg in
> many cases) is 70 dB worse than the traditional 20log(N) PN scaling?
>
> On Sat, Sep 15, 2018 at 11:40 AM Richard (Rick) Karlquist <
> ***@karlquist.com> wrote:
>
>> Another great posting from Attila that keeps the S/N ratio
>> on this list high.
>>
>> On 9/15/2018 3:26 AM, Attila Kinali wrote:
>>
>>> possible logic family for the task. Otherwise the harmonics of the
>>> switching of the FF will down-mix high frequency white noise down
>>> to the signal band (this is the reason for the 10*log(N) noise scaling
>>> of digital divider that Egan[1] and Calosso/Rubiola[2] and a few others
>>> mentioned).
>>
>> Wow, I never knew this in 45 years of designing synthesizers!
>> I do remember that some of the frequency counter engineers at HP
>> talked about noise aliasing. I think this is another way of
>> describing the same problem.
>>
>> About 10 years ago, the frequency synthesizer chip vendors started
>> talking about a Figure of Merit (FOM) that predicted phase noise floor,
>> and it also included the 10 LOG N noise scaling. An application
>> engineer at ADI told me this was a characteristic of the sampling phase
>> detector that all these chips used. But I always wondered if the
>> frequency divider could come into play. The way FOM is defined,
>> it doesn't distinguish between phase detector and divider noise.
>>
>> At Agilent, we used to make a lot of lab demos using a Centellax
>> (now Microsemi AKA Microchip) frequency divider that could divide by any
>> number between 8 and 511 up to 10 GHz. It was absolutely fabulous for
>> dividing 10 GHz down to 2.5 GHz. But 20 LOG N quit working if I tried
>> to divide down to 50 MHz. Now you have explained it.
>>>
>>> If you divide by something that is not a power of 2, then it is important
>>> that each stage produces an output waveform with a 50% duty cycle.
>> Otherwise
>>> flicker noise which has been up-mixed by a previous stage, will be
>> down-mixed
>>> into the signal band, increasing the close-in phase-noise.
>>
>> Wow, another thing I never knew. The conventional wisdom was to
>> divide by any number (even or odd) and then follow that divider
>> with a divide by 2 flip flop to get 50%. Now, that is in question.
>> The now correct answer is to us a variable modulus prescaler to
>> divide by P and P+1, controlled by a toggle flip flop to make
>> half the divisions at P and half at P+1.
>>
>> Does anyone else have experience with these issues?
>>
>> Rick N6RK
>>
>>
>> _______________________________________________
>> time-nuts mailing list -- time-***@lists.febo.com
>> To unsubscribe, go to
>> http://lists.febo.com/mailman/listinfo/time-nuts_lists.febo.com
>> and follow the instructions there.
>>
> _______________________________________________
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Gerhard Hoffmann
2018-09-16 20:08:19 UTC
Permalink
Am 15.09.2018 um 17:38 schrieb Richard (Rick) Karlquist:
>
>> If you divide by something that is not a power of 2, then it is
>> important
>> that each stage produces an output waveform with a 50% duty cycle.
>> Otherwise
>> flicker noise which has been up-mixed by a previous stage, will be
>> down-mixed
>> into the signal band, increasing the close-in phase-noise.
>
> Wow, another thing I never knew.  The conventional wisdom was to
> divide by any number (even or odd) and then follow that divider
> with a divide by 2 flip flop to get 50%.  Now, that is in question.
> The now correct answer is to us a variable modulus prescaler to
> divide by P and P+1, controlled by a toggle flip flop to make
> half the divisions at P and half at P+1.

Resynchronize the output of the divider to the undivided clock with
another D-FF
and everything but that last D-FF will fall out of the equation for
phase noise.

I'm also not a fan of using slowish, slew-rate challenged  logic as a
replacement
for a low pass. When I want a low pass, I make it from nice,
time-invariant RLC.

regards, Gerhard.



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Attila Kinali
2018-09-16 21:11:41 UTC
Permalink
On Sun, 16 Sep 2018 22:08:19 +0200
Gerhard Hoffmann <***@arcor.de> wrote:

> I'm also not a fan of using slowish, slew-rate challenged  logic as a
> replacement
> for a low pass. When I want a low pass, I make it from nice,
> time-invariant RLC.

Unfortunately, using a low pass after the divider will not
prevent the down-mixing. The down-mixing happens as an inherent
property of digital circuits. Any filtering you do afterwards
will be too late. If you want to have low noise, then the only
way is to produce a non-square wave signal. Or in other words:
use a divider built from harmonic mixers*.

Attila Kinali

* That is, if you don't like Λ-dividers or DDS
--
<JaberWorky> The bad part of Zurich is where the degenerates
throw DARK chocolate at you.

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Gerhard Hoffmann
2018-09-16 22:30:11 UTC
Permalink
Am 16.09.2018 um 23:11 schrieb Attila Kinali:
> On Sun, 16 Sep 2018 22:08:19 +0200
> Gerhard Hoffmann <***@arcor.de> wrote:
>
>> I'm also not a fan of using slowish, slew-rate challenged  logic as a
>> replacement
>> for a low pass. When I want a low pass, I make it from nice,
>> time-invariant RLC.
> Unfortunately, using a low pass after the divider will not
> prevent the down-mixing. The down-mixing happens as an inherent
> property of digital circuits. Any filtering you do afterwards
> will be too late. If you want to have low noise, then the only
> way is to produce a non-square wave signal. Or in other words:
> use a divider built from harmonic mixers*.
Why do you assume that slew-rate limited mixers are any
better than mixers with an ultra-short analog time window
for doing mess?

We should sort that out offline, we are just 20 miles apart?
I propose the Zwickel pub in Dudweiler; I'm there with the
mostly emerited Fraunhofer people on Friday evenings
now & then.        :-)  :-)  :-)
> * That is, if you don't like Λ-dividers or DDS
I do like DDS, and I don't see  a reason for the D/A converters
in front of the mixers. D/A converters remove the fun when you
can just instantiate a multiplier.

Cheers,

Gerhard



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Attila Kinali
2018-09-16 21:06:06 UTC
Permalink
Moin,

On Sat, 15 Sep 2018 08:38:55 -0700
"Richard (Rick) Karlquist" <***@karlquist.com> wrote:

> On 9/15/2018 3:26 AM, Attila Kinali wrote:
>
> > possible logic family for the task. Otherwise the harmonics of the
> > switching of the FF will down-mix high frequency white noise down
> > to the signal band (this is the reason for the 10*log(N) noise scaling
> > of digital divider that Egan[1] and Calosso/Rubiola[2] and a few others
> > mentioned).
>
> Wow, I never knew this in 45 years of designing synthesizers!
> I do remember that some of the frequency counter engineers at HP
> talked about noise aliasing. I think this is another way of
> describing the same problem.

Yes. This effect has been known for a few decades at least.
What kind of puzzles me is, that I have not seen a mathematically
sound explanation of it, so far. People talk of aliasing and sampling,
but do not describe where the sampling happens in the first place.
After all, it's a time-continuous system and as such, there is no
sampling. One could look at it as a (sub-harmonic) mixing system,
but even that analogy falls short, as there is no second input.
It also fails at describing why there is not infinite energy being
down-mixed, as the resulting harmonic sum does not converge.

If someone knows of a description that goes beyond handwavy arguments,
I would very much appreciate hearing of them.

The only way to explain the effect in a rigorous way, that I could
figure out, is to apply Hajimiri and Lee's Impulse Sensitivity Function[1],
and adapt from the oscillators they discribed to general periodic systems.
(The step, as one can guess, is small, but hic sunt dracones)
Doing this, it becomes obvious that the down-mixing is an inherent
property of all systems that use or generate non-sinusoidal waveforms.
It is this ISF that is the source of the down-mixing/aliasing effect,
as it has a periodic waveform of sharp spikes.

As the ISF is probably (this is my intuition and I have, unfortunately,
no proof of this) related to the derivative of the produced output waveform,
it becomes important to limit the slew rate of the output, to introduce
a second pole in the ISF and thus limit the number of harmonics.
Yet, it is also important to keep the input slew rate high, in order to
keep the width/height of the ISF pulses low.

A partial discussion of this can be found in the paper I presented
at IFCS earlier this year[2]. Unfortunately, the write-up is not
nice and I only realized after the deadline that I should have
all written it using a different approach. Sorry for that.
If something is not clear, do not hesitate to send me an email.

> About 10 years ago, the frequency synthesizer chip vendors started
> talking about a Figure of Merit (FOM) that predicted phase noise floor,
> and it also included the 10 LOG N noise scaling. An application
> engineer at ADI told me this was a characteristic of the sampling phase
> detector that all these chips used. But I always wondered if the
> frequency divider could come into play. The way FOM is defined,
> it doesn't distinguish between phase detector and divider noise.

The 10*log(N) also applies to the phase detector in PLL chips,
where N becomes the ratio of the phase detector bandwidth divided
by the phase detector input frequency.

Given that the phase noise is dominated by the input source' phase
noise, there will be no appreciatable difference in whether the
down-mixing happens in the divider or the phase detector, as long
as the bandwidth of all components is the same. If the bandwidth
is different, we get into something akin Collins' zero crossing
detector[3] where appropriately designed stages with different
input bandwidths limit the energy that is down-mixed.

> At Agilent, we used to make a lot of lab demos using a Centellax
> (now Microsemi AKA Microchip) frequency divider that could divide by any
> number between 8 and 511 up to 10 GHz. It was absolutely fabulous for
> dividing 10 GHz down to 2.5 GHz. But 20 LOG N quit working if I tried
> to divide down to 50 MHz. Now you have explained it.

Hmm? Are you implying those chips somehow were able to give
a 20*log(N) phase noise behaviour? If so, do you know how
they achieved such a feat?


> > If you divide by something that is not a power of 2, then it is important
> > that each stage produces an output waveform with a 50% duty cycle. Otherwise
> > flicker noise which has been up-mixed by a previous stage, will be down-mixed
> > into the signal band, increasing the close-in phase-noise.
>
> Wow, another thing I never knew.

I do not think that anyone was aware of this. A least I do not remember
seeing this being mentioned in any of the papers I have read. I, myself,
stumbled over it by accident. I was trying to design a sine-to-square
wave converter and wanted to understand what happend to the noise.
Especially the AM to PM conversion that a few people here have mentioned
a few times. I was looking at Claudio's measurement [4, page 28] and,
after applying Hajimir and Lee's ISF, I could (mathematically) explain
everything but what Enrico so nicely labled as "bump". None of the
explanations that I exchanged with Enrico, Claudio, Magnus and a few
other people made sense with the complete data. An external influence
didn't make sense as the flicker noise went from a straight ~6dB/oct line
to a straight ~3db/oct line below 25MHz. This hunch got stronger when
Claudio shared the complete circuit they used with me(see figure 3 in [2]).
The feedback circuit, which stabilizes duty cycle, has a -3dB frequency
of 0.28Hz, which is exactly the frequency where the bump is. And below
it, the flicker noise behavior seems to go back to approximately 6dB/oct.
For a complete explanation, see my paper[2] section 5.D "Scaling in a
Multi-Stage Sine-to-Square Converter."


> The conventional wisdom was to
> divide by any number (even or odd) and then follow that divider
> with a divide by 2 flip flop to get 50%. Now, that is in question.
> The now correct answer is to us a variable modulus prescaler to
> divide by P and P+1, controlled by a toggle flip flop to make
> half the divisions at P and half at P+1.

I don't think the modulus prescaler is a good approach.
It will help reduce flicker noise, at the price of incrased
white noise, as the two division values will generate two
frequency spikes in the ISF that are close to each other.
There is probably some residual even harmonic content due to
the switching betwen the two scaler values, which will increase
flicker noise, not as much as having non-50% duty cycle, but still.

The right way to do it is to use both edges in case of odd division
factors (as some of the divider circuits by Linear/Analog seem to do).
Alternatively generate a ramp/sine output, ie use a Λ-divider
or a DDS, as both have much lower harmonics content in the ISF
and thus do not suffer from the down-mixing as much. If a square
waveform is required afterwards, a square-to-sine converter with
approriate bandwidth for the output frequency will solve that.



Attila Kinali


[1] "A General Theory of Phase Noise in Electrical Oscillators,"
by Hajimir and Lee, 1998

[2] "A Physical Sine-to-Square Converter Noise Model,"
by Kinali, 2018

[3] "The Design of Low Jitter Hard Limiters," by Collins, 1996

[4] http://rubiola.org/pdf-slides/2016T-EFTF--Noise-in-digital-electronics.pdf
--
<JaberWorky> The bad part of Zurich is where the degenerates
throw DARK chocolate at you.

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Dana Whitlow
2018-09-16 21:33:55 UTC
Permalink
I'd been thinking, in an admittedly non-rigorous sort of way, about this
matter for some years.

As I see it, it is certainly true that the phase of an oscillator's output
is a continuous funciton
of time. It could be described as a continuous ramp, whose slope
corresponds to the frequency,
and with a little bit of non-flat random noise superimposed on it.

Now if you square up the waveform and do digital things with it (such as
freq dividing, digital
phase detection, etc), you are really only glimpsing the phase noise at
transition times, and
are blind in between. Thus the very process amounts to sampling the phase
noise waveform
with a sampling phase detector. This view suggests that all the phase
noise power is aliased
and folded back into the band ranging from DC to Fsamp / 2, where Fsamp is
the frequency
of the waveform after frequency division. This is why the time domain
jitter of the oscillator's
waveform is unchanged by "perfect" frequency division (or multiplication).

It is why I wonder about the wisdom of doing phase comparison at
unnecessarily low frequency-
all that noise would seem to be scrunched down into a bandwidth of half the
comparison frequency.

Does this explanation help, and how does it sit with those of you who have
more expertise
than I?

Dana




On Sun, Sep 16, 2018 at 4:06 PM, Attila Kinali <***@kinali.ch> wrote:

> Moin,
>
> On Sat, 15 Sep 2018 08:38:55 -0700
> "Richard (Rick) Karlquist" <***@karlquist.com> wrote:
>
> > On 9/15/2018 3:26 AM, Attila Kinali wrote:
> >
> > > possible logic family for the task. Otherwise the harmonics of the
> > > switching of the FF will down-mix high frequency white noise down
> > > to the signal band (this is the reason for the 10*log(N) noise scaling
> > > of digital divider that Egan[1] and Calosso/Rubiola[2] and a few others
> > > mentioned).
> >
> > Wow, I never knew this in 45 years of designing synthesizers!
> > I do remember that some of the frequency counter engineers at HP
> > talked about noise aliasing. I think this is another way of
> > describing the same problem.
>
> Yes. This effect has been known for a few decades at least.
> What kind of puzzles me is, that I have not seen a mathematically
> sound explanation of it, so far. People talk of aliasing and sampling,
> but do not describe where the sampling happens in the first place.
> After all, it's a time-continuous system and as such, there is no
> sampling. One could look at it as a (sub-harmonic) mixing system,
> but even that analogy falls short, as there is no second input.
> It also fails at describing why there is not infinite energy being
> down-mixed, as the resulting harmonic sum does not converge.
>
> If someone knows of a description that goes beyond handwavy arguments,
> I would very much appreciate hearing of them.
>
> The only way to explain the effect in a rigorous way, that I could
> figure out, is to apply Hajimiri and Lee's Impulse Sensitivity Function[1],
> and adapt from the oscillators they discribed to general periodic systems.
> (The step, as one can guess, is small, but hic sunt dracones)
> Doing this, it becomes obvious that the down-mixing is an inherent
> property of all systems that use or generate non-sinusoidal waveforms.
> It is this ISF that is the source of the down-mixing/aliasing effect,
> as it has a periodic waveform of sharp spikes.
>
> As the ISF is probably (this is my intuition and I have, unfortunately,
> no proof of this) related to the derivative of the produced output
> waveform,
> it becomes important to limit the slew rate of the output, to introduce
> a second pole in the ISF and thus limit the number of harmonics.
> Yet, it is also important to keep the input slew rate high, in order to
> keep the width/height of the ISF pulses low.
>
> A partial discussion of this can be found in the paper I presented
> at IFCS earlier this year[2]. Unfortunately, the write-up is not
> nice and I only realized after the deadline that I should have
> all written it using a different approach. Sorry for that.
> If something is not clear, do not hesitate to send me an email.
>
> > About 10 years ago, the frequency synthesizer chip vendors started
> > talking about a Figure of Merit (FOM) that predicted phase noise floor,
> > and it also included the 10 LOG N noise scaling. An application
> > engineer at ADI told me this was a characteristic of the sampling phase
> > detector that all these chips used. But I always wondered if the
> > frequency divider could come into play. The way FOM is defined,
> > it doesn't distinguish between phase detector and divider noise.
>
> The 10*log(N) also applies to the phase detector in PLL chips,
> where N becomes the ratio of the phase detector bandwidth divided
> by the phase detector input frequency.
>
> Given that the phase noise is dominated by the input source' phase
> noise, there will be no appreciatable difference in whether the
> down-mixing happens in the divider or the phase detector, as long
> as the bandwidth of all components is the same. If the bandwidth
> is different, we get into something akin Collins' zero crossing
> detector[3] where appropriately designed stages with different
> input bandwidths limit the energy that is down-mixed.
>
> > At Agilent, we used to make a lot of lab demos using a Centellax
> > (now Microsemi AKA Microchip) frequency divider that could divide by any
> > number between 8 and 511 up to 10 GHz. It was absolutely fabulous for
> > dividing 10 GHz down to 2.5 GHz. But 20 LOG N quit working if I tried
> > to divide down to 50 MHz. Now you have explained it.
>
> Hmm? Are you implying those chips somehow were able to give
> a 20*log(N) phase noise behaviour? If so, do you know how
> they achieved such a feat?
>
>
> > > If you divide by something that is not a power of 2, then it is
> important
> > > that each stage produces an output waveform with a 50% duty cycle.
> Otherwise
> > > flicker noise which has been up-mixed by a previous stage, will be
> down-mixed
> > > into the signal band, increasing the close-in phase-noise.
> >
> > Wow, another thing I never knew.
>
> I do not think that anyone was aware of this. A least I do not remember
> seeing this being mentioned in any of the papers I have read. I, myself,
> stumbled over it by accident. I was trying to design a sine-to-square
> wave converter and wanted to understand what happend to the noise.
> Especially the AM to PM conversion that a few people here have mentioned
> a few times. I was looking at Claudio's measurement [4, page 28] and,
> after applying Hajimir and Lee's ISF, I could (mathematically) explain
> everything but what Enrico so nicely labled as "bump". None of the
> explanations that I exchanged with Enrico, Claudio, Magnus and a few
> other people made sense with the complete data. An external influence
> didn't make sense as the flicker noise went from a straight ~6dB/oct line
> to a straight ~3db/oct line below 25MHz. This hunch got stronger when
> Claudio shared the complete circuit they used with me(see figure 3 in [2]).
> The feedback circuit, which stabilizes duty cycle, has a -3dB frequency
> of 0.28Hz, which is exactly the frequency where the bump is. And below
> it, the flicker noise behavior seems to go back to approximately 6dB/oct.
> For a complete explanation, see my paper[2] section 5.D "Scaling in a
> Multi-Stage Sine-to-Square Converter."
>
>
> > The conventional wisdom was to
> > divide by any number (even or odd) and then follow that divider
> > with a divide by 2 flip flop to get 50%. Now, that is in question.
> > The now correct answer is to us a variable modulus prescaler to
> > divide by P and P+1, controlled by a toggle flip flop to make
> > half the divisions at P and half at P+1.
>
> I don't think the modulus prescaler is a good approach.
> It will help reduce flicker noise, at the price of incrased
> white noise, as the two division values will generate two
> frequency spikes in the ISF that are close to each other.
> There is probably some residual even harmonic content due to
> the switching betwen the two scaler values, which will increase
> flicker noise, not as much as having non-50% duty cycle, but still.
>
> The right way to do it is to use both edges in case of odd division
> factors (as some of the divider circuits by Linear/Analog seem to do).
> Alternatively generate a ramp/sine output, ie use a Λ-divider
> or a DDS, as both have much lower harmonics content in the ISF
> and thus do not suffer from the down-mixing as much. If a square
> waveform is required afterwards, a square-to-sine converter with
> approriate bandwidth for the output frequency will solve that.
>
>
>
> Attila Kinali
>
>
> [1] "A General Theory of Phase Noise in Electrical Oscillators,"
> by Hajimir and Lee, 1998
>
> [2] "A Physical Sine-to-Square Converter Noise Model,"
> by Kinali, 2018
>
> [3] "The Design of Low Jitter Hard Limiters," by Collins, 1996
>
> [4] http://rubiola.org/pdf-slides/2016T-EFTF--Noise-in-digital-
> electronics.pdf
> --
> <JaberWorky> The bad part of Zurich is where the degenerates
> throw DARK chocolate at you.
>
> _______________________________________________
> time-nuts mailing list -- time-***@lists.febo.com
> To unsubscribe, go to http://lists.febo.com/mailman/
> listinfo/time-nuts_lists.febo.com
> and follow the instructions there.
>
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Bob kb8tq
2018-09-17 02:15:34 UTC
Permalink
Hi

It’s pretty easy to demonstrate that squaring up a sine wave, even with fairly simple
circuits does not create crazy phase noise issues. People have been doing it successfully
for a lot of years. In general faster saturated logic produces lower noise floors than slower
logic.

Bob

> On Sep 16, 2018, at 4:33 PM, Dana Whitlow <***@gmail.com> wrote:
>
> I'd been thinking, in an admittedly non-rigorous sort of way, about this
> matter for some years.
>
> As I see it, it is certainly true that the phase of an oscillator's output
> is a continuous funciton
> of time. It could be described as a continuous ramp, whose slope
> corresponds to the frequency,
> and with a little bit of non-flat random noise superimposed on it.
>
> Now if you square up the waveform and do digital things with it (such as
> freq dividing, digital
> phase detection, etc), you are really only glimpsing the phase noise at
> transition times, and
> are blind in between. Thus the very process amounts to sampling the phase
> noise waveform
> with a sampling phase detector. This view suggests that all the phase
> noise power is aliased
> and folded back into the band ranging from DC to Fsamp / 2, where Fsamp is
> the frequency
> of the waveform after frequency division. This is why the time domain
> jitter of the oscillator's
> waveform is unchanged by "perfect" frequency division (or multiplication).
>
> It is why I wonder about the wisdom of doing phase comparison at
> unnecessarily low frequency-
> all that noise would seem to be scrunched down into a bandwidth of half the
> comparison frequency.
>
> Does this explanation help, and how does it sit with those of you who have
> more expertise
> than I?
>
> Dana
>
>
>
>
> On Sun, Sep 16, 2018 at 4:06 PM, Attila Kinali <***@kinali.ch> wrote:
>
>> Moin,
>>
>> On Sat, 15 Sep 2018 08:38:55 -0700
>> "Richard (Rick) Karlquist" <***@karlquist.com> wrote:
>>
>>> On 9/15/2018 3:26 AM, Attila Kinali wrote:
>>>
>>>> possible logic family for the task. Otherwise the harmonics of the
>>>> switching of the FF will down-mix high frequency white noise down
>>>> to the signal band (this is the reason for the 10*log(N) noise scaling
>>>> of digital divider that Egan[1] and Calosso/Rubiola[2] and a few others
>>>> mentioned).
>>>
>>> Wow, I never knew this in 45 years of designing synthesizers!
>>> I do remember that some of the frequency counter engineers at HP
>>> talked about noise aliasing. I think this is another way of
>>> describing the same problem.
>>
>> Yes. This effect has been known for a few decades at least.
>> What kind of puzzles me is, that I have not seen a mathematically
>> sound explanation of it, so far. People talk of aliasing and sampling,
>> but do not describe where the sampling happens in the first place.
>> After all, it's a time-continuous system and as such, there is no
>> sampling. One could look at it as a (sub-harmonic) mixing system,
>> but even that analogy falls short, as there is no second input.
>> It also fails at describing why there is not infinite energy being
>> down-mixed, as the resulting harmonic sum does not converge.
>>
>> If someone knows of a description that goes beyond handwavy arguments,
>> I would very much appreciate hearing of them.
>>
>> The only way to explain the effect in a rigorous way, that I could
>> figure out, is to apply Hajimiri and Lee's Impulse Sensitivity Function[1],
>> and adapt from the oscillators they discribed to general periodic systems.
>> (The step, as one can guess, is small, but hic sunt dracones)
>> Doing this, it becomes obvious that the down-mixing is an inherent
>> property of all systems that use or generate non-sinusoidal waveforms.
>> It is this ISF that is the source of the down-mixing/aliasing effect,
>> as it has a periodic waveform of sharp spikes.
>>
>> As the ISF is probably (this is my intuition and I have, unfortunately,
>> no proof of this) related to the derivative of the produced output
>> waveform,
>> it becomes important to limit the slew rate of the output, to introduce
>> a second pole in the ISF and thus limit the number of harmonics.
>> Yet, it is also important to keep the input slew rate high, in order to
>> keep the width/height of the ISF pulses low.
>>
>> A partial discussion of this can be found in the paper I presented
>> at IFCS earlier this year[2]. Unfortunately, the write-up is not
>> nice and I only realized after the deadline that I should have
>> all written it using a different approach. Sorry for that.
>> If something is not clear, do not hesitate to send me an email.
>>
>>> About 10 years ago, the frequency synthesizer chip vendors started
>>> talking about a Figure of Merit (FOM) that predicted phase noise floor,
>>> and it also included the 10 LOG N noise scaling. An application
>>> engineer at ADI told me this was a characteristic of the sampling phase
>>> detector that all these chips used. But I always wondered if the
>>> frequency divider could come into play. The way FOM is defined,
>>> it doesn't distinguish between phase detector and divider noise.
>>
>> The 10*log(N) also applies to the phase detector in PLL chips,
>> where N becomes the ratio of the phase detector bandwidth divided
>> by the phase detector input frequency.
>>
>> Given that the phase noise is dominated by the input source' phase
>> noise, there will be no appreciatable difference in whether the
>> down-mixing happens in the divider or the phase detector, as long
>> as the bandwidth of all components is the same. If the bandwidth
>> is different, we get into something akin Collins' zero crossing
>> detector[3] where appropriately designed stages with different
>> input bandwidths limit the energy that is down-mixed.
>>
>>> At Agilent, we used to make a lot of lab demos using a Centellax
>>> (now Microsemi AKA Microchip) frequency divider that could divide by any
>>> number between 8 and 511 up to 10 GHz. It was absolutely fabulous for
>>> dividing 10 GHz down to 2.5 GHz. But 20 LOG N quit working if I tried
>>> to divide down to 50 MHz. Now you have explained it.
>>
>> Hmm? Are you implying those chips somehow were able to give
>> a 20*log(N) phase noise behaviour? If so, do you know how
>> they achieved such a feat?
>>
>>
>>>> If you divide by something that is not a power of 2, then it is
>> important
>>>> that each stage produces an output waveform with a 50% duty cycle.
>> Otherwise
>>>> flicker noise which has been up-mixed by a previous stage, will be
>> down-mixed
>>>> into the signal band, increasing the close-in phase-noise.
>>>
>>> Wow, another thing I never knew.
>>
>> I do not think that anyone was aware of this. A least I do not remember
>> seeing this being mentioned in any of the papers I have read. I, myself,
>> stumbled over it by accident. I was trying to design a sine-to-square
>> wave converter and wanted to understand what happend to the noise.
>> Especially the AM to PM conversion that a few people here have mentioned
>> a few times. I was looking at Claudio's measurement [4, page 28] and,
>> after applying Hajimir and Lee's ISF, I could (mathematically) explain
>> everything but what Enrico so nicely labled as "bump". None of the
>> explanations that I exchanged with Enrico, Claudio, Magnus and a few
>> other people made sense with the complete data. An external influence
>> didn't make sense as the flicker noise went from a straight ~6dB/oct line
>> to a straight ~3db/oct line below 25MHz. This hunch got stronger when
>> Claudio shared the complete circuit they used with me(see figure 3 in [2]).
>> The feedback circuit, which stabilizes duty cycle, has a -3dB frequency
>> of 0.28Hz, which is exactly the frequency where the bump is. And below
>> it, the flicker noise behavior seems to go back to approximately 6dB/oct.
>> For a complete explanation, see my paper[2] section 5.D "Scaling in a
>> Multi-Stage Sine-to-Square Converter."
>>
>>
>>> The conventional wisdom was to
>>> divide by any number (even or odd) and then follow that divider
>>> with a divide by 2 flip flop to get 50%. Now, that is in question.
>>> The now correct answer is to us a variable modulus prescaler to
>>> divide by P and P+1, controlled by a toggle flip flop to make
>>> half the divisions at P and half at P+1.
>>
>> I don't think the modulus prescaler is a good approach.
>> It will help reduce flicker noise, at the price of incrased
>> white noise, as the two division values will generate two
>> frequency spikes in the ISF that are close to each other.
>> There is probably some residual even harmonic content due to
>> the switching betwen the two scaler values, which will increase
>> flicker noise, not as much as having non-50% duty cycle, but still.
>>
>> The right way to do it is to use both edges in case of odd division
>> factors (as some of the divider circuits by Linear/Analog seem to do).
>> Alternatively generate a ramp/sine output, ie use a Λ-divider
>> or a DDS, as both have much lower harmonics content in the ISF
>> and thus do not suffer from the down-mixing as much. If a square
>> waveform is required afterwards, a square-to-sine converter with
>> approriate bandwidth for the output frequency will solve that.
>>
>>
>>
>> Attila Kinali
>>
>>
>> [1] "A General Theory of Phase Noise in Electrical Oscillators,"
>> by Hajimir and Lee, 1998
>>
>> [2] "A Physical Sine-to-Square Converter Noise Model,"
>> by Kinali, 2018
>>
>> [3] "The Design of Low Jitter Hard Limiters," by Collins, 1996
>>
>> [4] http://rubiola.org/pdf-slides/2016T-EFTF--Noise-in-digital-
>> electronics.pdf
>> --
>> <JaberWorky> The bad part of Zurich is where the degenerates
>> throw DARK chocolate at you.
>>
>> _______________________________________________
>> time-nuts mailing list -- time-***@lists.febo.com
>> To unsubscribe, go to http://lists.febo.com/mailman/
>> listinfo/time-nuts_lists.febo.com
>> and follow the instructions there.
>>
> _______________________________________________
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and
Dana Whitlow
2018-09-17 05:37:43 UTC
Permalink
The act of squaring up the waveform alone might not do much harm, depending
on the extent
to which the phase noise on said waveform has already been filtered off.
But it's mainly when
the signal gets divided down by large ratios that the difference would
become really noticeable.

For example, take the case of 10 MHz starting frequency; the phase noise
several MHz out
is likely to be nil. But divide the 10 MHz down to, say, 1 Hz; then
there's likely to be quite a
lot of phase noise within "folding range" of many Nyquist bands about 1 Hz.

This, again, is why I wonder so much about our efforts in re-synthesizing
higher frequencies from
the 1PPS from GPS receivers. I don't know much the architecture of GPS
receivers, but it seems
to me it would sure be nice if there were some convenient way to extract a
clean signal at the
chipping rate, for use in generating standard reference frequencies.

Dana




On Sun, Sep 16, 2018 at 9:15 PM, Bob kb8tq <***@n1k.org> wrote:

> Hi
>
> It’s pretty easy to demonstrate that squaring up a sine wave, even with
> fairly simple
> circuits does not create crazy phase noise issues. People have been doing
> it successfully
> for a lot of years. In general faster saturated logic produces lower noise
> floors than slower
> logic.
>
> Bob
>
> > On Sep 16, 2018, at 4:33 PM, Dana Whitlow <***@gmail.com> wrote:
> >
> > I'd been thinking, in an admittedly non-rigorous sort of way, about this
> > matter for some years.
> >
> > As I see it, it is certainly true that the phase of an oscillator's
> output
> > is a continuous funciton
> > of time. It could be described as a continuous ramp, whose slope
> > corresponds to the frequency,
> > and with a little bit of non-flat random noise superimposed on it.
> >
> > Now if you square up the waveform and do digital things with it (such as
> > freq dividing, digital
> > phase detection, etc), you are really only glimpsing the phase noise at
> > transition times, and
> > are blind in between. Thus the very process amounts to sampling the
> phase
> > noise waveform
> > with a sampling phase detector. This view suggests that all the phase
> > noise power is aliased
> > and folded back into the band ranging from DC to Fsamp / 2, where Fsamp
> is
> > the frequency
> > of the waveform after frequency division. This is why the time domain
> > jitter of the oscillator's
> > waveform is unchanged by "perfect" frequency division (or
> multiplication).
> >
> > It is why I wonder about the wisdom of doing phase comparison at
> > unnecessarily low frequency-
> > all that noise would seem to be scrunched down into a bandwidth of half
> the
> > comparison frequency.
> >
> > Does this explanation help, and how does it sit with those of you who
> have
> > more expertise
> > than I?
> >
> > Dana
> >
> >
> >
> >
> > On Sun, Sep 16, 2018 at 4:06 PM, Attila Kinali <***@kinali.ch> wrote:
> >
> >> Moin,
> >>
> >> On Sat, 15 Sep 2018 08:38:55 -0700
> >> "Richard (Rick) Karlquist" <***@karlquist.com> wrote:
> >>
> >>> On 9/15/2018 3:26 AM, Attila Kinali wrote:
> >>>
> >>>> possible logic family for the task. Otherwise the harmonics of the
> >>>> switching of the FF will down-mix high frequency white noise down
> >>>> to the signal band (this is the reason for the 10*log(N) noise scaling
> >>>> of digital divider that Egan[1] and Calosso/Rubiola[2] and a few
> others
> >>>> mentioned).
> >>>
> >>> Wow, I never knew this in 45 years of designing synthesizers!
> >>> I do remember that some of the frequency counter engineers at HP
> >>> talked about noise aliasing. I think this is another way of
> >>> describing the same problem.
> >>
> >> Yes. This effect has been known for a few decades at least.
> >> What kind of puzzles me is, that I have not seen a mathematically
> >> sound explanation of it, so far. People talk of aliasing and sampling,
> >> but do not describe where the sampling happens in the first place.
> >> After all, it's a time-continuous system and as such, there is no
> >> sampling. One could look at it as a (sub-harmonic) mixing system,
> >> but even that analogy falls short, as there is no second input.
> >> It also fails at describing why there is not infinite energy being
> >> down-mixed, as the resulting harmonic sum does not converge.
> >>
> >> If someone knows of a description that goes beyond handwavy arguments,
> >> I would very much appreciate hearing of them.
> >>
> >> The only way to explain the effect in a rigorous way, that I could
> >> figure out, is to apply Hajimiri and Lee's Impulse Sensitivity
> Function[1],
> >> and adapt from the oscillators they discribed to general periodic
> systems.
> >> (The step, as one can guess, is small, but hic sunt dracones)
> >> Doing this, it becomes obvious that the down-mixing is an inherent
> >> property of all systems that use or generate non-sinusoidal waveforms.
> >> It is this ISF that is the source of the down-mixing/aliasing effect,
> >> as it has a periodic waveform of sharp spikes.
> >>
> >> As the ISF is probably (this is my intuition and I have, unfortunately,
> >> no proof of this) related to the derivative of the produced output
> >> waveform,
> >> it becomes important to limit the slew rate of the output, to introduce
> >> a second pole in the ISF and thus limit the number of harmonics.
> >> Yet, it is also important to keep the input slew rate high, in order to
> >> keep the width/height of the ISF pulses low.
> >>
> >> A partial discussion of this can be found in the paper I presented
> >> at IFCS earlier this year[2]. Unfortunately, the write-up is not
> >> nice and I only realized after the deadline that I should have
> >> all written it using a different approach. Sorry for that.
> >> If something is not clear, do not hesitate to send me an email.
> >>
> >>> About 10 years ago, the frequency synthesizer chip vendors started
> >>> talking about a Figure of Merit (FOM) that predicted phase noise floor,
> >>> and it also included the 10 LOG N noise scaling. An application
> >>> engineer at ADI told me this was a characteristic of the sampling phase
> >>> detector that all these chips used. But I always wondered if the
> >>> frequency divider could come into play. The way FOM is defined,
> >>> it doesn't distinguish between phase detector and divider noise.
> >>
> >> The 10*log(N) also applies to the phase detector in PLL chips,
> >> where N becomes the ratio of the phase detector bandwidth divided
> >> by the phase detector input frequency.
> >>
> >> Given that the phase noise is dominated by the input source' phase
> >> noise, there will be no appreciatable difference in whether the
> >> down-mixing happens in the divider or the phase detector, as long
> >> as the bandwidth of all components is the same. If the bandwidth
> >> is different, we get into something akin Collins' zero crossing
> >> detector[3] where appropriately designed stages with different
> >> input bandwidths limit the energy that is down-mixed.
> >>
> >>> At Agilent, we used to make a lot of lab demos using a Centellax
> >>> (now Microsemi AKA Microchip) frequency divider that could divide by
> any
> >>> number between 8 and 511 up to 10 GHz. It was absolutely fabulous for
> >>> dividing 10 GHz down to 2.5 GHz. But 20 LOG N quit working if I tried
> >>> to divide down to 50 MHz. Now you have explained it.
> >>
> >> Hmm? Are you implying those chips somehow were able to give
> >> a 20*log(N) phase noise behaviour? If so, do you know how
> >> they achieved such a feat?
> >>
> >>
> >>>> If you divide by something that is not a power of 2, then it is
> >> important
> >>>> that each stage produces an output waveform with a 50% duty cycle.
> >> Otherwise
> >>>> flicker noise which has been up-mixed by a previous stage, will be
> >> down-mixed
> >>>> into the signal band, increasing the close-in phase-noise.
> >>>
> >>> Wow, another thing I never knew.
> >>
> >> I do not think that anyone was aware of this. A least I do not remember
> >> seeing this being mentioned in any of the papers I have read. I, myself,
> >> stumbled over it by accident. I was trying to design a sine-to-square
> >> wave converter and wanted to understand what happend to the noise.
> >> Especially the AM to PM conversion that a few people here have mentioned
> >> a few times. I was looking at Claudio's measurement [4, page 28] and,
> >> after applying Hajimir and Lee's ISF, I could (mathematically) explain
> >> everything but what Enrico so nicely labled as "bump". None of the
> >> explanations that I exchanged with Enrico, Claudio, Magnus and a few
> >> other people made sense with the complete data. An external influence
> >> didn't make sense as the flicker noise went from a straight ~6dB/oct
> line
> >> to a straight ~3db/oct line below 25MHz. This hunch got stronger when
> >> Claudio shared the complete circuit they used with me(see figure 3 in
> [2]).
> >> The feedback circuit, which stabilizes duty cycle, has a -3dB frequency
> >> of 0.28Hz, which is exactly the frequency where the bump is. And below
> >> it, the flicker noise behavior seems to go back to approximately
> 6dB/oct.
> >> For a complete explanation, see my paper[2] section 5.D "Scaling in a
> >> Multi-Stage Sine-to-Square Converter."
> >>
> >>
> >>> The conventional wisdom was to
> >>> divide by any number (even or odd) and then follow that divider
> >>> with a divide by 2 flip flop to get 50%. Now, that is in question.
> >>> The now correct answer is to us a variable modulus prescaler to
> >>> divide by P and P+1, controlled by a toggle flip flop to make
> >>> half the divisions at P and half at P+1.
> >>
> >> I don't think the modulus prescaler is a good approach.
> >> It will help reduce flicker noise, at the price of incrased
> >> white noise, as the two division values will generate two
> >> frequency spikes in the ISF that are close to each other.
> >> There is probably some residual even harmonic content due to
> >> the switching betwen the two scaler values, which will increase
> >> flicker noise, not as much as having non-50% duty cycle, but still.
> >>
> >> The right way to do it is to use both edges in case of odd division
> >> factors (as some of the divider circuits by Linear/Analog seem to do).
> >> Alternatively generate a ramp/sine output, ie use a Λ-divider
> >> or a DDS, as both have much lower harmonics content in the ISF
> >> and thus do not suffer from the down-mixing as much. If a square
> >> waveform is required afterwards, a square-to-sine converter with
> >> approriate bandwidth for the output frequency will solve that.
> >>
> >>
> >>
> >> Attila Kinali
> >>
> >>
> >> [1] "A General Theory of Phase Noise in Electrical Oscillators,"
> >> by Hajimir and Lee, 1998
> >>
> >> [2] "A Physical Sine-to-Square Converter Noise Model,"
> >> by Kinali, 2018
> >>
> >> [3] "The Design of Low Jitter Hard Limiters," by Collins, 1996
> >>
> >> [4] http://rubiola.org/pdf-slides/2016T-EFTF--Noise-in-digital-
> >> electronics.pdf
> >> --
> >> <JaberWorky> The bad part of Zurich is where the degenerates
> >> throw DARK chocolate at you.
> >>
> >> _______________________________________________
> >> time-nuts mailing list -- time-***@lists.febo.com
> >> To unsubscribe, go to http://lists.febo.com/mailman/
> >> listinfo/time-nuts_lists.febo.com
> >> and follow the instructions there.
> >>
> > _______________________________________________
> > time-nuts mailing list -- time-***@lists.febo.com
> > To unsubscribe, go to http://lists.febo.com/mailman/
> listinfo/time-nuts_lists.febo.com
> > and follow the instructions there.
>
>
> _______________________________________________
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> To unsubscribe, go to http://lists.febo.com/mailman/
> listinfo/time-nuts_lists.febo.com
> and follow the instructions there.
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Bob kb8tq
2018-09-17 14:24:16 UTC
Permalink
Hi

For moderate division ratios ( like 100 MHz down to 1 MHz ), the 20 log N stuff holds
pretty well ….

Bob

> On Sep 17, 2018, at 12:37 AM, Dana Whitlow <***@gmail.com> wrote:
>
> The act of squaring up the waveform alone might not do much harm, depending
> on the extent
> to which the phase noise on said waveform has already been filtered off.
> But it's mainly when
> the signal gets divided down by large ratios that the difference would
> become really noticeable.
>
> For example, take the case of 10 MHz starting frequency; the phase noise
> several MHz out
> is likely to be nil. But divide the 10 MHz down to, say, 1 Hz; then
> there's likely to be quite a
> lot of phase noise within "folding range" of many Nyquist bands about 1 Hz.
>
> This, again, is why I wonder so much about our efforts in re-synthesizing
> higher frequencies from
> the 1PPS from GPS receivers. I don't know much the architecture of GPS
> receivers, but it seems
> to me it would sure be nice if there were some convenient way to extract a
> clean signal at the
> chipping rate, for use in generating standard reference frequencies.
>
> Dana
>
>
>
>
> On Sun, Sep 16, 2018 at 9:15 PM, Bob kb8tq <***@n1k.org> wrote:
>
>> Hi
>>
>> It’s pretty easy to demonstrate that squaring up a sine wave, even with
>> fairly simple
>> circuits does not create crazy phase noise issues. People have been doing
>> it successfully
>> for a lot of years. In general faster saturated logic produces lower noise
>> floors than slower
>> logic.
>>
>> Bob
>>
>>> On Sep 16, 2018, at 4:33 PM, Dana Whitlow <***@gmail.com> wrote:
>>>
>>> I'd been thinking, in an admittedly non-rigorous sort of way, about this
>>> matter for some years.
>>>
>>> As I see it, it is certainly true that the phase of an oscillator's
>> output
>>> is a continuous funciton
>>> of time. It could be described as a continuous ramp, whose slope
>>> corresponds to the frequency,
>>> and with a little bit of non-flat random noise superimposed on it.
>>>
>>> Now if you square up the waveform and do digital things with it (such as
>>> freq dividing, digital
>>> phase detection, etc), you are really only glimpsing the phase noise at
>>> transition times, and
>>> are blind in between. Thus the very process amounts to sampling the
>> phase
>>> noise waveform
>>> with a sampling phase detector. This view suggests that all the phase
>>> noise power is aliased
>>> and folded back into the band ranging from DC to Fsamp / 2, where Fsamp
>> is
>>> the frequency
>>> of the waveform after frequency division. This is why the time domain
>>> jitter of the oscillator's
>>> waveform is unchanged by "perfect" frequency division (or
>> multiplication).
>>>
>>> It is why I wonder about the wisdom of doing phase comparison at
>>> unnecessarily low frequency-
>>> all that noise would seem to be scrunched down into a bandwidth of half
>> the
>>> comparison frequency.
>>>
>>> Does this explanation help, and how does it sit with those of you who
>> have
>>> more expertise
>>> than I?
>>>
>>> Dana
>>>
>>>
>>>
>>>
>>> On Sun, Sep 16, 2018 at 4:06 PM, Attila Kinali <***@kinali.ch> wrote:
>>>
>>>> Moin,
>>>>
>>>> On Sat, 15 Sep 2018 08:38:55 -0700
>>>> "Richard (Rick) Karlquist" <***@karlquist.com> wrote:
>>>>
>>>>> On 9/15/2018 3:26 AM, Attila Kinali wrote:
>>>>>
>>>>>> possible logic family for the task. Otherwise the harmonics of the
>>>>>> switching of the FF will down-mix high frequency white noise down
>>>>>> to the signal band (this is the reason for the 10*log(N) noise scaling
>>>>>> of digital divider that Egan[1] and Calosso/Rubiola[2] and a few
>> others
>>>>>> mentioned).
>>>>>
>>>>> Wow, I never knew this in 45 years of designing synthesizers!
>>>>> I do remember that some of the frequency counter engineers at HP
>>>>> talked about noise aliasing. I think this is another way of
>>>>> describing the same problem.
>>>>
>>>> Yes. This effect has been known for a few decades at least.
>>>> What kind of puzzles me is, that I have not seen a mathematically
>>>> sound explanation of it, so far. People talk of aliasing and sampling,
>>>> but do not describe where the sampling happens in the first place.
>>>> After all, it's a time-continuous system and as such, there is no
>>>> sampling. One could look at it as a (sub-harmonic) mixing system,
>>>> but even that analogy falls short, as there is no second input.
>>>> It also fails at describing why there is not infinite energy being
>>>> down-mixed, as the resulting harmonic sum does not converge.
>>>>
>>>> If someone knows of a description that goes beyond handwavy arguments,
>>>> I would very much appreciate hearing of them.
>>>>
>>>> The only way to explain the effect in a rigorous way, that I could
>>>> figure out, is to apply Hajimiri and Lee's Impulse Sensitivity
>> Function[1],
>>>> and adapt from the oscillators they discribed to general periodic
>> systems.
>>>> (The step, as one can guess, is small, but hic sunt dracones)
>>>> Doing this, it becomes obvious that the down-mixing is an inherent
>>>> property of all systems that use or generate non-sinusoidal waveforms.
>>>> It is this ISF that is the source of the down-mixing/aliasing effect,
>>>> as it has a periodic waveform of sharp spikes.
>>>>
>>>> As the ISF is probably (this is my intuition and I have, unfortunately,
>>>> no proof of this) related to the derivative of the produced output
>>>> waveform,
>>>> it becomes important to limit the slew rate of the output, to introduce
>>>> a second pole in the ISF and thus limit the number of harmonics.
>>>> Yet, it is also important to keep the input slew rate high, in order to
>>>> keep the width/height of the ISF pulses low.
>>>>
>>>> A partial discussion of this can be found in the paper I presented
>>>> at IFCS earlier this year[2]. Unfortunately, the write-up is not
>>>> nice and I only realized after the deadline that I should have
>>>> all written it using a different approach. Sorry for that.
>>>> If something is not clear, do not hesitate to send me an email.
>>>>
>>>>> About 10 years ago, the frequency synthesizer chip vendors started
>>>>> talking about a Figure of Merit (FOM) that predicted phase noise floor,
>>>>> and it also included the 10 LOG N noise scaling. An application
>>>>> engineer at ADI told me this was a characteristic of the sampling phase
>>>>> detector that all these chips used. But I always wondered if the
>>>>> frequency divider could come into play. The way FOM is defined,
>>>>> it doesn't distinguish between phase detector and divider noise.
>>>>
>>>> The 10*log(N) also applies to the phase detector in PLL chips,
>>>> where N becomes the ratio of the phase detector bandwidth divided
>>>> by the phase detector input frequency.
>>>>
>>>> Given that the phase noise is dominated by the input source' phase
>>>> noise, there will be no appreciatable difference in whether the
>>>> down-mixing happens in the divider or the phase detector, as long
>>>> as the bandwidth of all components is the same. If the bandwidth
>>>> is different, we get into something akin Collins' zero crossing
>>>> detector[3] where appropriately designed stages with different
>>>> input bandwidths limit the energy that is down-mixed.
>>>>
>>>>> At Agilent, we used to make a lot of lab demos using a Centellax
>>>>> (now Microsemi AKA Microchip) frequency divider that could divide by
>> any
>>>>> number between 8 and 511 up to 10 GHz. It was absolutely fabulous for
>>>>> dividing 10 GHz down to 2.5 GHz. But 20 LOG N quit working if I tried
>>>>> to divide down to 50 MHz. Now you have explained it.
>>>>
>>>> Hmm? Are you implying those chips somehow were able to give
>>>> a 20*log(N) phase noise behaviour? If so, do you know how
>>>> they achieved such a feat?
>>>>
>>>>
>>>>>> If you divide by something that is not a power of 2, then it is
>>>> important
>>>>>> that each stage produces an output waveform with a 50% duty cycle.
>>>> Otherwise
>>>>>> flicker noise which has been up-mixed by a previous stage, will be
>>>> down-mixed
>>>>>> into the signal band, increasing the close-in phase-noise.
>>>>>
>>>>> Wow, another thing I never knew.
>>>>
>>>> I do not think that anyone was aware of this. A least I do not remember
>>>> seeing this being mentioned in any of the papers I have read. I, myself,
>>>> stumbled over it by accident. I was trying to design a sine-to-square
>>>> wave converter and wanted to understand what happend to the noise.
>>>> Especially the AM to PM conversion that a few people here have mentioned
>>>> a few times. I was looking at Claudio's measurement [4, page 28] and,
>>>> after applying Hajimir and Lee's ISF, I could (mathematically) explain
>>>> everything but what Enrico so nicely labled as "bump". None of the
>>>> explanations that I exchanged with Enrico, Claudio, Magnus and a few
>>>> other people made sense with the complete data. An external influence
>>>> didn't make sense as the flicker noise went from a straight ~6dB/oct
>> line
>>>> to a straight ~3db/oct line below 25MHz. This hunch got stronger when
>>>> Claudio shared the complete circuit they used with me(see figure 3 in
>> [2]).
>>>> The feedback circuit, which stabilizes duty cycle, has a -3dB frequency
>>>> of 0.28Hz, which is exactly the frequency where the bump is. And below
>>>> it, the flicker noise behavior seems to go back to approximately
>> 6dB/oct.
>>>> For a complete explanation, see my paper[2] section 5.D "Scaling in a
>>>> Multi-Stage Sine-to-Square Converter."
>>>>
>>>>
>>>>> The conventional wisdom was to
>>>>> divide by any number (even or odd) and then follow that divider
>>>>> with a divide by 2 flip flop to get 50%. Now, that is in question.
>>>>> The now correct answer is to us a variable modulus prescaler to
>>>>> divide by P and P+1, controlled by a toggle flip flop to make
>>>>> half the divisions at P and half at P+1.
>>>>
>>>> I don't think the modulus prescaler is a good approach.
>>>> It will help reduce flicker noise, at the price of incrased
>>>> white noise, as the two division values will generate two
>>>> frequency spikes in the ISF that are close to each other.
>>>> There is probably some residual even harmonic content due to
>>>> the switching betwen the two scaler values, which will increase
>>>> flicker noise, not as much as having non-50% duty cycle, but still.
>>>>
>>>> The right way to do it is to use both edges in case of odd division
>>>> factors (as some of the divider circuits by Linear/Analog seem to do).
>>>> Alternatively generate a ramp/sine output, ie use a Λ-divider
>>>> or a DDS, as both have much lower harmonics content in the ISF
>>>> and thus do not suffer from the down-mixing as much. If a square
>>>> waveform is required afterwards, a square-to-sine converter with
>>>> approriate bandwidth for the output frequency will solve that.
>>>>
>>>>
>>>>
>>>> Attila Kinali
>>>>
>>>>
>>>> [1] "A General Theory of Phase Noise in Electrical Oscillators,"
>>>> by Hajimir and Lee, 1998
>>>>
>>>> [2] "A Physical Sine-to-Square Converter Noise Model,"
>>>> by Kinali, 2018
>>>>
>>>> [3] "The Design of Low Jitter Hard Limiters," by Collins, 1996
>>>>
>>>> [4] http://rubiola.org/pdf-slides/2016T-EFTF--Noise-in-digital-
>>>> electronics.pdf
>>>> --
>>>> <JaberWorky> The bad part of Zurich is where the degenerates
>>>> throw DARK chocolate at you.
>>>>
>>>> _______________________________________________
>>>> time-nuts mailing list -- time-***@lists.febo.com
>>>> To unsubscribe, go to http://lists.febo.com/mailman/
>>>> listinfo/time-nuts_lists.febo.com
>>>> and follow the instructions there.
>>>>
>>> _______________________________________________
>>> time-nuts mailing list -- time-***@lists.febo.com
>>> To unsubscribe, go to http://lists.febo.com/mailman/
>> listinfo/time-nuts_lists.febo.com
>>> and follow the instructions there.
>>
>>
>> _______________________________________________
>> time-nuts mailing list -- time-***@lists.febo.com
>> To unsubscribe, go to http://lists.febo.com/mailman/
>> listinfo/time-nuts_lists.febo.com
>> and follow the instructions there.
>>
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Attila Kinali
2018-10-10 15:04:02 UTC
Permalink
On Mon, 17 Sep 2018 00:37:43 -0500
Dana Whitlow <***@gmail.com> wrote:

> For example, take the case of 10 MHz starting frequency; the phase noise
> several MHz out
> is likely to be nil. But divide the 10 MHz down to, say, 1 Hz; then
> there's likely to be quite a
> lot of phase noise within "folding range" of many Nyquist bands about 1 Hz.

For most low-noise systems, the white noise floor is dominated by
the thermal (Johnson) noise due to the 50 Ohm source impedance.
Although, one could say this noise is very low, it is wrong to
assume it can be ignored. Jitter, for a low-noise 10MHz system,
is dominated by the white noise and very little of the contribution
is due to flicker noise (unless you go for very long integration times).

> This, again, is why I wonder so much about our efforts in re-synthesizing
> higher frequencies from
> the 1PPS from GPS receivers. I don't know much the architecture of GPS
> receivers, but it seems
> to me it would sure be nice if there were some convenient way to extract a
> clean signal at the
> chipping rate, for use in generating standard reference frequencies.

There are systems that do that, but one has to use signals from
multiple satellites to get the noise down. But for proper combination
of multiple signals one has to calculate a fix. Hence it is easier
to just check the reference oscillators phase against the fix.
And synthesizing from PPS is exactly this process of referencing
the 10MHz oscillator to the calculated fixes.

Attila Kinali

--
Science is made up of so many things that appear obvious
after they are explained. -- Pardot Kynes

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ed breya
2018-09-16 23:01:10 UTC
Permalink
Atilla wrote: "Yes. This effect has been known for a few decades at
least. What kind of puzzles me is, that I have not seen a mathematically
sound explanation of it, so far. People talk of aliasing and sampling,
but do not describe where the sampling happens in the first place. After
all, it's a time-continuous system and as such, there is no sampling.
One could look at it as a (sub-harmonic) mixing system, but even that
analogy falls short, as there is no second input. If someone knows of a
description that goes beyond handwavy arguments, I would very much
appreciate hearing of them."

I can only offer a handwavy suggestion, or food for thought, regarding
digital dividers of all sorts.

Regardless of the type of divider or process used, the devices within
have finite gain, so imperfect isolation between the output activity and
input. Whatever is happening downstream in a divider chain can provide a
delayed, topology- and pattern-dependent signal back to the input,
containing the associated frequency content. The issue of course, is how
big the effect may be.

I don't know if this sort of thing is trivial or has already been
included somehow in the rigorous and theoretical studies, but I know
it's there, having observed such anomalies over the years. I've never
had a situation where the effect was big enough to prevent something
from working right, just casual observations that made me think about
what's going on.

You can probably observe it easily with enough dynamic range. Say, set
up an ECL FF to divide by two, and AC couple everything for ground
reference. Put in an RF clock signal - sine, square, doesn't matter -
and look at this input signal with a spectrum analyzer (don't worry too
much about impedance matching - just get the clock signal big enough to
toggle). You should see the strong clock and its harmonics, as expected,
and if you dig deep enough, should be able to see the one-half frequency
that shouldn't exist with a perfect FF. Now, how it gets there may be
due to a number of reasons like ground loops or power supply coupling,
but some of it is going right through the device from out to in.

Ed



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Attila Kinali
2018-09-17 11:45:02 UTC
Permalink
On Sun, 16 Sep 2018 23:06:06 +0200
Attila Kinali <***@kinali.ch> wrote:

> [2] "A Physical Sine-to-Square Converter Noise Model,"
> by Kinali, 2018

Oops.. I forgot to add the link to the pdf, sorry
http://people.mpi-inf.mpg.de/~adogan/pubs/IFCS2018_comparator_noise.pdf


Attila Kinali
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use without that foundation.
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Mattia Rizzi
2018-09-20 10:31:01 UTC
Permalink
Hi Attila, everyone,
very interesting discussion!

>People talk of aliasing and sampling,
but do not describe where the sampling happens in the first place.
After all, it's a time-continuous system and as such, there is no
sampling.

I would say that the sampling occurs when you're using only a slice of an
input signal. For instance, If you're using only the zero-crossing slice
of a sinewave to produce a divided version rather than the full envelope.
It's a matter of how you process information in your circuit.

>"A Physical Sine-to-Square Converter Noise Model,"
> by Kinali, 2018

I read the paper, very interesting as well!
I have a minor remark, in the paper you relate the ISF (let's say
"sampling window") to the output slew rate of the comparator. I would say
that the sampling window should be related to the comparator input stage
bandwidth. If you have an high bandwidth input stage (e.g. 5 GHz) followed
by a slew rate limited output stage (e.g. 100 MHz) , high frequency noise
will trigger the output circuit and aliasing it. Viceversa, if you have a
low bandwidth input stage, even if the output stage is very fast, you don't
get input noise aliasing.

cheers
Mattia




Il giorno lun 17 set 2018 alle ore 13:46 Attila Kinali <***@kinali.ch>
ha scritto:

> On Sun, 16 Sep 2018 23:06:06 +0200
> Attila Kinali <***@kinali.ch> wrote:
>
> > [2] "A Physical Sine-to-Square Converter Noise Model,"
> > by Kinali, 2018
>
> Oops.. I forgot to add the link to the pdf, sorry
> http://people.mpi-inf.mpg.de/~adogan/pubs/IFCS2018_comparator_noise.pdf
>
>
> Attila Kinali
> --
> It is upon moral qualities that a society is ultimately founded. All
> the prosperity and technological sophistication in the world is of no
> use without that foundation.
> -- Miss Matheson, The Diamond Age, Neal Stephenson
>
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Attila Kinali
2018-10-10 14:54:25 UTC
Permalink
Salut Mattia,

On Thu, 20 Sep 2018 12:31:01 +0200
Mattia Rizzi <***@gmail.com> wrote:

> > People talk of aliasing and sampling,
> > but do not describe where the sampling happens in the first place.
> > After all, it's a time-continuous system and as such, there is no
> > sampling.
>
> I would say that the sampling occurs when you're using only a slice of an
> input signal. For instance, If you're using only the zero-crossing slice
> of a sinewave to produce a divided version rather than the full envelope.
> It's a matter of how you process information in your circuit.

Yes. That's the basic way how the sampling/noise-aliasing happens.
I just wonder why nobody (as far as I am aware of) has described
this process in detail. It looks obvious and if you look at the
general information theory/signal processing literature, it almost
falls out of the basic text books.

> >"A Physical Sine-to-Square Converter Noise Model,"
> > by Kinali, 2018
>
> I read the paper, very interesting as well!
> I have a minor remark, in the paper you relate the ISF (let's say
> "sampling window") to the output slew rate of the comparator. I would say
> that the sampling window should be related to the comparator input stage
> bandwidth. If you have an high bandwidth input stage (e.g. 5 GHz) followed
> by a slew rate limited output stage (e.g. 100 MHz) , high frequency noise
> will trigger the output circuit and aliasing it. Viceversa, if you have a
> low bandwidth input stage, even if the output stage is very fast, you don't
> get input noise aliasing.

Yes, exactly! Though, you have to look at a comparator IC as a multi-stage
system, where each gain-stage represents one "comparator" in my paper.
Hence the first gain stage already aliases the noise from its whole
bandwidth, which can be a lot of noise if the BW is large.

Hmm.. I probably should have made it more clear that the model I
defined applies only to single gain stages and not to whole components.


Attila Kinali

--
Science is made up of so many things that appear obvious
after they are explained. -- Pardot Kynes

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Poul-Henning Kamp
2018-10-10 15:20:56 UTC
Permalink
--------
In message <***@kinali.ch>, Attila Kinali w
rites:

>> >"A Physical Sine-to-Square Converter Noise Model,"
>> > by Kinali, 2018
>>
>[...]
>Hence the first gain stage already aliases the noise from its whole
>bandwidth, which can be a lot of noise if the BW is large.

Some years ago I spent a lot of time trying to find a way to
"oversample" single-shots of the 3rd zero-crossing of Loran-C
signals.

My finding was that of all the technologies available, the simple
comparator was the worst, because it only "looks" at a very tiny
time-slice around the actual zero-crossing, and thus is needlessly
sensitive to noise.

To make matters worse, the window is always late, it cannot be
symmetric, because at least some electrons have to move in the
opposite direction before the comparator changes state. HP has
interesting info about this in an old app-note on TI counters.

If the incoming curve-shape is unknown, that is the only thing one
can do, but when the curve-shape is known to be a sine or a loran-C,
better results can be had with a wider time window.

The final version of my code (This was SDR with an ADC directly on
the antenna) found the optimal least-square match between the sampled
signal and the theoretical signal for a configurable time-window,
produced the zero crossing from the theoretical signal.

Best performance was around 1/6-th period, which I'm sure there was
a reason for, but I gave up looking for it.

I have not found a way to implement it in the analog domain.

--
Poul-Henning Kamp | UNIX since Zilog Zeus 3.20
***@FreeBSD.ORG | TCP/IP since RFC 956
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Never attribute to malice what can adequately be explained by incompetence.

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Azelio Boriani
2018-10-10 19:55:32 UTC
Permalink
How many samples of the Loran input signal in that 1/6th of the period?
On Wed, Oct 10, 2018 at 5:22 PM Poul-Henning Kamp <***@phk.freebsd.dk> wrote:
>
> --------
> In message <***@kinali.ch>, Attila Kinali w
> rites:
>
> >> >"A Physical Sine-to-Square Converter Noise Model,"
> >> > by Kinali, 2018
> >>
> >[...]
> >Hence the first gain stage already aliases the noise from its whole
> >bandwidth, which can be a lot of noise if the BW is large.
>
> Some years ago I spent a lot of time trying to find a way to
> "oversample" single-shots of the 3rd zero-crossing of Loran-C
> signals.
>
> My finding was that of all the technologies available, the simple
> comparator was the worst, because it only "looks" at a very tiny
> time-slice around the actual zero-crossing, and thus is needlessly
> sensitive to noise.
>
> To make matters worse, the window is always late, it cannot be
> symmetric, because at least some electrons have to move in the
> opposite direction before the comparator changes state. HP has
> interesting info about this in an old app-note on TI counters.
>
> If the incoming curve-shape is unknown, that is the only thing one
> can do, but when the curve-shape is known to be a sine or a loran-C,
> better results can be had with a wider time window.
>
> The final version of my code (This was SDR with an ADC directly on
> the antenna) found the optimal least-square match between the sampled
> signal and the theoretical signal for a configurable time-window,
> produced the zero crossing from the theoretical signal.
>
> Best performance was around 1/6-th period, which I'm sure there was
> a reason for, but I gave up looking for it.
>
> I have not found a way to implement it in the analog domain.
>
> --
> Poul-Henning Kamp | UNIX since Zilog Zeus 3.20
> ***@FreeBSD.ORG | TCP/IP since RFC 956
> FreeBSD committer | BSD since 4.3-tahoe
> Never attribute to malice what can adequately be explained by incompetence.
>
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Poul-Henning Kamp
2018-10-10 20:20:09 UTC
Permalink
--------
In message <CAPjwOuK90ncvoD1kkcSCmmVtCjGy2qNwt90tG=***@mail.gmail.com>
, Azelio Boriani writes:

>How many samples of the Loran input signal in that 1/6th of the period?

Not many: At 5MHz sample rate it was 8 samples.

--
Poul-Henning Kamp | UNIX since Zilog Zeus 3.20
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Achim Gratz
2018-09-20 21:45:27 UTC
Permalink
Attila Kinali writes:
> Yes. This effect has been known for a few decades at least. What kind
> of puzzles me is, that I have not seen a mathematically sound
> explanation of it, so far.

I'm afraid I can't help with the rigor, but the fundamentals seem simple
enough to me.

> People talk of aliasing and sampling, but do not describe where the
> sampling happens in the first place. After all, it's a
> time-continuous system and as such, there is no sampling.

That may be quibbling over terminology and definitions not actually
specified in those papers. Localization in the frequency domain
requires periodicity in the time domain (by definition) and moving
spectral features around can be done by convolution of the noise
spectrum with a localized signal (not necessarily of compact support,
but assume for the moment it is so you get a clearly defined pivot
frequency). That means you need to do multiplication in the time domain
with something periodic, so all you need to produce noise folding is for
instance a periodically varying NTF. I guess we can tick that box in
all instances you've mentioned.

> One could look at it as a (sub-harmonic) mixing system, but
> even that analogy falls short, as there is no second input.

Does it even matter if you call it a "second input"?

Reading the Egan paper I guess the line of arguments that leads to
"sampling", "mixing" and "aliasing" getting used is that the
periodically varying NTF (or ISF if you like) looks and acts
sufficiently like a Dirac comb that you can use sampling theory to
interpret the results. Or conversely, that you can take the results and
postulate a sampling process with a sampling aperture that happens to
look virtually identical to (one period of) your NTF. This seems not
much different than what gets routinely done when reasoning about
real-world systems that do "proper" sampling, but of course do not sport
a perfect dirac pulse sampling aperture.

> It also fails at describing why there is not infinite energy being
> down-mixed, as the resulting harmonic sum does not converge.

The actual integral or sum to compute would likely be governed by
something sinc-like, so convergence would eventually still happen with
any physically realizable input. That assumes you don't already need to
start with some generalization of the Fourier transform that has more
strictly defined convergence behaviour.

[…]
>> > If you divide by something that is not a power of 2, then it is important
>> > that each stage produces an output waveform with a 50% duty cycle. Otherwise
>> > flicker noise which has been up-mixed by a previous stage, will be down-mixed
>> > into the signal band, increasing the close-in phase-noise.
>>
>> Wow, another thing I never knew.
>
> I do not think that anyone was aware of this.

Funnily a paper I just read in TCAS-I (February 2017) by Pepe and
Andreani about phase noise in harmonic oscillators seems to mention this
(I think) as a known result w.r.t. flicker noise upconversion and
generalize (ref. eq. 90) on previous results for several particular
oscillator topologies which guarantee the necessary conditions. There
is also lots of discussion about the relation to the ISF and results in
conjunction with it that goes right above my head. The direction their
math is taking looks intriguing, so maybe you are able to glean
something from it to use. Whether there's any pre-existing link of
those results specifically to frequency dividers I don't know.


Regards,
Achim.
--
+<[Q+ Matrix-12 WAVE#46+305 Neuron microQkb Andromeda XTk Blofeld]>+

SD adaptations for KORG EX-800 and Poly-800MkII V0.9:
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and
Attila Kinali
2018-10-10 14:47:55 UTC
Permalink
On Thu, 20 Sep 2018 23:45:27 +0200
Achim Gratz <***@nexgo.de> wrote:

> Attila Kinali writes:
> > People talk of aliasing and sampling, but do not describe where the
> > sampling happens in the first place. After all, it's a
> > time-continuous system and as such, there is no sampling.
>
> That may be quibbling over terminology and definitions not actually
> specified in those papers. Localization in the frequency domain
> requires periodicity in the time domain (by definition) and moving
> spectral features around can be done by convolution of the noise
> spectrum with a localized signal (not necessarily of compact support,
> but assume for the moment it is so you get a clearly defined pivot
> frequency). That means you need to do multiplication in the time domain
> with something periodic, so all you need to produce noise folding is for
> instance a periodically varying NTF. I guess we can tick that box in
> all instances you've mentioned.

Exactly. But sofar nobody has properly specified what the other
term of the multiplication is.

> > One could look at it as a (sub-harmonic) mixing system, but
> > even that analogy falls short, as there is no second input.
>
> Does it even matter if you call it a "second input"?

Not really, but if you want to argue about the noise folding
process as being a sub-harmonic mixing process, then you need
to specify what the second signal is that does the mixing.
Which in turn is again specifying the two terms of the multiplication
process as above.

> > It also fails at describing why there is not infinite energy being
> > down-mixed, as the resulting harmonic sum does not converge.
>
> The actual integral or sum to compute would likely be governed by
> something sinc-like, so convergence would eventually still happen with
> any physically realizable input. That assumes you don't already need to
> start with some generalization of the Fourier transform that has more
> strictly defined convergence behaviour.

This is exactly one of the things that made me stumble when I first
went through the relevant literature. A sinc pulse-train in time
domain becomes a rectangular pulse-train in the frequency domain,
whose amplitude decays with 1/f. This means, the folded down noise
is a sum of terms decaying with 1/f. But this sum does not converge,
ie it goes to infinity. One has to add an addtional filter of some
sort that increases the rate of decay to 1/f^2 for the sum to converge.


> Funnily a paper I just read in TCAS-I (February 2017) by Pepe and
> Andreani about phase noise in harmonic oscillators seems to mention this
> (I think) as a known result w.r.t. flicker noise upconversion and

Oh.. thanks! I somehow missed this paper. The results look indeed
interesting. But I have to spend some time to work through the math
in order to fully understand it.


Attila Kinali


--
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after they are explained. -- Pardot Kynes

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Magnus Danielson
2018-11-09 22:34:21 UTC
Permalink
On 9/16/18 11:06 PM, Attila Kinali wrote:
> Moin,
>
> On Sat, 15 Sep 2018 08:38:55 -0700
> "Richard (Rick) Karlquist" <***@karlquist.com> wrote:
>
>> On 9/15/2018 3:26 AM, Attila Kinali wrote:
>>
>>> possible logic family for the task. Otherwise the harmonics of the
>>> switching of the FF will down-mix high frequency white noise down
>>> to the signal band (this is the reason for the 10*log(N) noise scaling
>>> of digital divider that Egan[1] and Calosso/Rubiola[2] and a few others
>>> mentioned).
>>
>> Wow, I never knew this in 45 years of designing synthesizers!
>> I do remember that some of the frequency counter engineers at HP
>> talked about noise aliasing. I think this is another way of
>> describing the same problem.
>
> Yes. This effect has been known for a few decades at least.
> What kind of puzzles me is, that I have not seen a mathematically
> sound explanation of it, so far. People talk of aliasing and sampling,
> but do not describe where the sampling happens in the first place.
> After all, it's a time-continuous system and as such, there is no
> sampling. One could look at it as a (sub-harmonic) mixing system,
> but even that analogy falls short, as there is no second input.0
> It also fails at describing why there is not infinite energy being
> down-mixed, as the resulting harmonic sum does not converge.

A single diode mixes, hence no secondary port. The double-balanced mixer
is what you get when using transformers and four diodes to cancel out
the input signals, but a single diode suffice if you can handle the
original signal and the mix products.

There will be no infinite energy, for very trivial reasons. While you
might think that integration (or actually summation) of a 1/n series
would not converge, the actual life situation is not a 1/n series, since
the rise/fall time creates a -6 dB/Oct slope in itself, resulting in a
-12 dB/Oct slope for higher N, and hence the full series converge. This
also means that the mixed down noise has finite result. It is thus the
trivial bandwidth limitation of the system kicking in. Obvious from
basic EMC training.

> If someone knows of a description that goes beyond handwavy arguments,
> I would very much appreciate hearing of them.
>
> The only way to explain the effect in a rigorous way, that I could
> figure out, is to apply Hajimiri and Lee's Impulse Sensitivity Function[1],
> and adapt from the oscillators they discribed to general periodic systems.
> (The step, as one can guess, is small, but hic sunt dracones)
> Doing this, it becomes obvious that the down-mixing is an inherent
> property of all systems that use or generate non-sinusoidal waveforms.
> It is this ISF that is the source of the down-mixing/aliasing effect,
> as it has a periodic waveform of sharp spikes.

Downmixing is a result of non-linearity. Feed a perfect sine in there,
and it will downmix on overtones for you. That is how non-linearities
such as diodes work. Look on the Taylor expansion of the exponential
function or logaritmic function and think what pure sine + noise will do
there. It is usually easier to analyze by modeling the noise as a small
sine. Each x^n in the Taylor expansion will create a rich set of
products, consider the noise sine to be near a perfect multiple of the
base sine and out pops these products.

> As the ISF is probably (this is my intuition and I have, unfortunately,
> no proof of this) related to the derivative of the produced output waveform,
> it becomes important to limit the slew rate of the output, to introduce
> a second pole in the ISF and thus limit the number of harmonics.
> Yet, it is also important to keep the input slew rate high, in order to
> keep the width/height of the ISF pulses low.
>
> A partial discussion of this can be found in the paper I presented
> at IFCS earlier this year[2]. Unfortunately, the write-up is not
> nice and I only realized after the deadline that I should have
> all written it using a different approach. Sorry for that.
> If something is not clear, do not hesitate to send me an email.
>
>> About 10 years ago, the frequency synthesizer chip vendors started
>> talking about a Figure of Merit (FOM) that predicted phase noise floor,
>> and it also included the 10 LOG N noise scaling. An application
>> engineer at ADI told me this was a characteristic of the sampling phase
>> detector that all these chips used. But I always wondered if the
>> frequency divider could come into play. The way FOM is defined,
>> it doesn't distinguish between phase detector and divider noise.
>
> The 10*log(N) also applies to the phase detector in PLL chips,
> where N becomes the ratio of the phase detector bandwidth divided
> by the phase detector input frequency.
>
> Given that the phase noise is dominated by the input source' phase
> noise, there will be no appreciatable difference in whether the
> down-mixing happens in the divider or the phase detector, as long
> as the bandwidth of all components is the same. If the bandwidth
> is different, we get into something akin Collins' zero crossing
> detector[3] where appropriately designed stages with different
> input bandwidths limit the energy that is down-mixed.
>
>> At Agilent, we used to make a lot of lab demos using a Centellax
>> (now Microsemi AKA Microchip) frequency divider that could divide by any
>> number between 8 and 511 up to 10 GHz. It was absolutely fabulous for
>> dividing 10 GHz down to 2.5 GHz. But 20 LOG N quit working if I tried
>> to divide down to 50 MHz. Now you have explained it.
>
> Hmm? Are you implying those chips somehow were able to give
> a 20*log(N) phase noise behaviour? If so, do you know how
> they achieved such a feat?

The phase noise scales with frequency this way. The time-noise is the
same, it's just that you now have N cycles between the occurrence of
time, so N times lower in amplitude or 20 log(N) in dB. However, that is
for a theoretically perfect divider, so eventually you hit the noise
floor of the divider. Perfectly well described in the NIST library.

>>> If you divide by something that is not a power of 2, then it is important
>>> that each stage produces an output waveform with a 50% duty cycle. Otherwise
>>> flicker noise which has been up-mixed by a previous stage, will be down-mixed
>>> into the signal band, increasing the close-in phase-noise.
>>
>> Wow, another thing I never knew.
>
> I do not think that anyone was aware of this. A least I do not remember
> seeing this being mentioned in any of the papers I have read.

Read the old NIST stuff, it's in there. This is also why they prefer to
do odd division and "clean up" with a separate divide by 2.

> I, myself,
> stumbled over it by accident. I was trying to design a sine-to-square
> wave converter and wanted to understand what happend to the noise.
> Especially the AM to PM conversion that a few people here have mentioned
> a few times. I was looking at Claudio's measurement [4, page 28] and,
> after applying Hajimir and Lee's ISF, I could (mathematically) explain
> everything but what Enrico so nicely labled as "bump". None of the
> explanations that I exchanged with Enrico, Claudio, Magnus and a few
> other people made sense with the complete data. An external influence
> didn't make sense as the flicker noise went from a straight ~6dB/oct line
> to a straight ~3db/oct line below 25MHz. This hunch got stronger when
> Claudio shared the complete circuit they used with me(see figure 3 in [2]).
> The feedback circuit, which stabilizes duty cycle, has a -3dB frequency
> of 0.28Hz, which is exactly the frequency where the bump is. And below
> it, the flicker noise behavior seems to go back to approximately 6dB/oct.
> For a complete explanation, see my paper[2] section 5.D "Scaling in a
> Multi-Stage Sine-to-Square Converter."

Not the first or the last time a control loop ads a hump. If made
simple, you get amplification gain. PLLs do it on their resonances for
instance, which is why they need to be well damped.

>> The conventional wisdom was to
>> divide by any number (even or odd) and then follow that divider
>> with a divide by 2 flip flop to get 50%. Now, that is in question.
>> The now correct answer is to us a variable modulus prescaler to
>> divide by P and P+1, controlled by a toggle flip flop to make
>> half the divisions at P and half at P+1.
>
> I don't think the modulus prescaler is a good approach.
> It will help reduce flicker noise, at the price of incrased
> white noise, as the two division values will generate two
> frequency spikes in the ISF that are close to each other.
> There is probably some residual even harmonic content due to
> the switching betwen the two scaler values, which will increase
> flicker noise, not as much as having non-50% duty cycle, but still.

It will just add systematic phase-noise. The divide by 2 rather
down-mixes with out of phase variants so it to some degree self-balance.
Also, 50% has zeros on even frequencies but as you shift away from 50%
you start to add power on even overtones. That's what PWM does for you.

> The right way to do it is to use both edges in case of odd division
> factors (as some of the divider circuits by Linear/Analog seem to do).
> Alternatively generate a ramp/sine output, ie use a Λ-divider
> or a DDS, as both have much lower harmonics content in the ISF
> and thus do not suffer from the down-mixing as much. If a square
> waveform is required afterwards, a square-to-sine converter with
> approriate bandwidth for the output frequency will solve that.

Sine with just sufficient bandwidth, then into square-to-sine converter.
No high-Q filters around.

Cheers,
Magnus

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Richard (Rick) Karlquist
2018-09-14 20:24:11 UTC
Permalink
I encountered these oscillators on a circuit I inherited
from another engineer. The spectrum of these is quite
dirty and they should only be considered as digital clock
oscillators. An additional annoyance is that they are
not marked with the frequency they are programmed to,
so if you have USB and LSB you'll have to put a dot
of paint on them or something to tell them apart.

Dividing by 4 or N will reduce spurs by 20 LOG N as
any time nut knows. If you get a programmable oscillator
at a frequency around 32 MHz and divide it down by 128
to ~253 kHz, you might get enough clean up for your
purposes. 20 LOG 128 = 42 dB.

Alternately, find a conventional clock
oscillator that can be divided by an even integer to hit
your BFO frequency. For example, 20 MHz divided by
78 = 256.4 kHz. 20 MHz divided by 80 = 250 kHz.
Divide by 39 followed by divide by 2 or divide by 40
followed by divide by 2, in order to get a square wave
at the output.

Rick N6RK

On 9/14/2018 9:14 AM, ***@cox.net wrote:
> Off topic for this list, but you guys are experts in oscillator noise!
>
> Playing with some mechanical filters. Need USB and LSB crystals for the BFO. No one seems to make crystals anymore, especially in the 253 KHz range!
>
> Looking at the DigiKey Cardinal programmable oscillators. Cheap and available: CPPC1LZ A5B6
>
> Anyone have an idea how noisy these would be after a division by 4 to get them in range?
>
> Thanks,
>
> N0UU
> _______________________________________________
> time-nuts mailing list -- time-***@lists.febo.com
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>

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ed breya
2018-09-14 23:04:53 UTC
Permalink
Those programmable oscillators look interesting. I went to Cardinal the
website to learn more, but they're pretty sparse on details. It looks
like they make all sorts of crystals, OC, TC, and VT XO modules, etc,
and these programmable ones, which are apparently PLL-based oscillators
locked to an XO. They don't say much more, but if you asked, maybe
they'd give some usable info.

There was also some mention of their own shortcomings with phase noise
and jitter, circa 2005, and how the later generations are much improved.

I'd say that since the programmed frequency is at least XO-based, then
its stability seems to be specified and can be good, but the noise etc
of the associated PLL inside does not seem to specified. It may be OK
for the application to just pick a certain frequency that would be
easier on the PLL (if you knew more about it and the XO frequency they
would use), and easy to divide down to your end results. I would wonder
what the few-off cost would be for the appropriate base parts and
programming.

They also seem to have custom crystal building service, which could be
very handy, depending on the cost. I've often needed oddball frequencies
for various projects, and wished it was easy and cheap to just order
some up.

Another trick you can try, that I've resorted to a number of times, is
to find two "standard" or common (or oddball ones that you happen to
already have) crystal frequencies that you can mix to get the desired
result. The combinations of various crystals and possible dividing
ratios may yield something close enough to tweak in. An EXCEL sheet can
help organize the info and choices.

Finally, of course, you can use DDS. This is nearly an ideal case for
this, since you want to make stuff around 250 kHz, but necessarily must
(for lack of in-range XOs) use a clock in the MHz region - maybe ten to
a hundred times higher than the output, so easy to get a good sine out.
Between the various XO clock frequencies available, and the program
choices in the DDS, it should be possible to come up with a nice scheme
to make whatever you want down in that range.

Ed

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Richard (Rick) Karlquist
2018-09-14 23:14:52 UTC
Permalink
>
> Finally, of course, you can use DDS. This is nearly an ideal case for

The trouble with a DDS is that you need a microcontroller with
software just to baby sit the thing.

Rick N6RK

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ed breya
2018-09-15 00:03:26 UTC
Permalink
Rick said:
"The trouble with a DDS is that you need a microcontroller with software
just to baby sit the thing."

Yes, I know what you mean. I wouldn't want to go through all that. I'm
picturing more like the small, cheap DDS boards that show up on ebay.
Maybe the right stuff could be found that can stand alone, for maybe a
tenth the cost of a custom crystal or XO.

I've always been kind of frustrated with not being able to readily use
most of the cool new technologies in ICs, due to the SMT packaging, and
the need for programming them via serial ports. I have saved a number of
comparatively old-school, obsolete DDS and PLL devices, because they are
parallel controlled, and can be hard-wired for fixed or limited functions.

Also, speaking of PLLs, maybe that would be the way to go for the OP -
depending on the particular frequencies needed, and the resulting
complexity of the divider(s).

Ed

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Mike Feher
2018-09-15 00:04:28 UTC
Permalink
Not when I built them in the late 60's and early 70's. All discrete. 73 -
Mike



Mike B. Feher, N4FS

89 Arnold Blvd.

Howell NJ 07731

848-245-9115



-----Original Message-----
From: time-nuts <time-nuts-***@lists.febo.com> On Behalf Of Richard
(Rick) Karlquist
Sent: Friday, September 14, 2018 7:15 PM
To: Discussion of precise time and frequency measurement
<time-***@lists.febo.com>; ed breya <***@telight.com>
Subject: Re: [time-nuts] Programmable clock for BFO use....noise



>

> Finally, of course, you can use DDS. This is nearly an ideal case for



The trouble with a DDS is that you need a microcontroller with software just
to baby sit the thing.



Rick N6RK



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paul swed
2018-09-15 01:06:43 UTC
Permalink
The beauty of a $2 arduino and a drop of code snitched from Engineer google.
OK enough of that back to the thread.
Regards
Paul
WB8TSL

On Fri, Sep 14, 2018 at 8:04 PM, Mike Feher <***@eozinc.com> wrote:

> Not when I built them in the late 60's and early 70's. All discrete. 73 -
> Mike
>
>
>
> Mike B. Feher, N4FS
>
> 89 Arnold Blvd.
>
> Howell NJ 07731
>
> 848-245-9115
>
>
>
> -----Original Message-----
> From: time-nuts <time-nuts-***@lists.febo.com> On Behalf Of Richard
> (Rick) Karlquist
> Sent: Friday, September 14, 2018 7:15 PM
> To: Discussion of precise time and frequency measurement
> <time-***@lists.febo.com>; ed breya <***@telight.com>
> Subject: Re: [time-nuts] Programmable clock for BFO use....noise
>
>
>
> >
>
> > Finally, of course, you can use DDS. This is nearly an ideal case for
>
>
>
> The trouble with a DDS is that you need a microcontroller with software
> just
> to baby sit the thing.
>
>
>
> Rick N6RK
>
>
>
> _______________________________________________
>
> time-nuts mailing list -- <mailto:time-***@lists.febo.com>
> time-***@lists.febo.com To unsubscribe, go to
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>
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Chris Waldrup
2018-09-16 17:22:05 UTC
Permalink
How about using a ProgRock on Hans Summers QRP Labs website? This is a programmable crystal replacement.

Chris
KD4PBJ

> On Sep 14, 2018, at 8:06 PM, paul swed <***@gmail.com> wrote:
>
> The beauty of a $2 arduino and a drop of code snitched from Engineer google.
> OK enough of that back to the thread.
> Regards
> Paul
> WB8TSL
>
>> On Fri, Sep 14, 2018 at 8:04 PM, Mike Feher <***@eozinc.com> wrote:
>>
>> Not when I built them in the late 60's and early 70's. All discrete. 73 -
>> Mike
>>
>>
>>
>> Mike B. Feher, N4FS
>>
>> 89 Arnold Blvd.
>>
>> Howell NJ 07731
>>
>> 848-245-9115
>>
>>
>>
>> -----Original Message-----
>> From: time-nuts <time-nuts-***@lists.febo.com> On Behalf Of Richard
>> (Rick) Karlquist
>> Sent: Friday, September 14, 2018 7:15 PM
>> To: Discussion of precise time and frequency measurement
>> <time-***@lists.febo.com>; ed breya <***@telight.com>
>> Subject: Re: [time-nuts] Programmable clock for BFO use....noise
>>
>>
>>
>>
>>> Finally, of course, you can use DDS. This is nearly an ideal case for
>>
>>
>>
>> The trouble with a DDS is that you need a microcontroller with software
>> just
>> to baby sit the thing.
>>
>>
>>
>> Rick N6RK
>>
>>
>>
>> _______________________________________________
>>
>> time-nuts mailing list -- <mailto:time-***@lists.febo.com>
>> time-***@lists.febo.com To unsubscribe, go to
>> <http://lists.febo.com/mailman/listinfo/time-nuts_lists.febo.com>
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>>
>> and follow the instructions there.
>>
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Magnus Danielson
2018-09-16 19:40:56 UTC
Permalink
Hi Chris,

On 09/16/2018 07:22 PM, Chris Waldrup wrote:
> How about using a ProgRock on Hans Summers QRP Labs website? This is a programmable crystal replacement.

I have one of those but have not had the time to put it up for a real
test. Also got the GPS module that should fit, as you can train it to
slave a PPS. It would be interesting to take the setup for a test-ride.

Need to clean the desk with other things in order to be able to focus on
fun projects like that.

Cheers,
Magnus

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Mark Goldberg
2018-09-16 18:00:58 UTC
Permalink
For a radio BFO you want something with low phase noise (low jitter). The
SI5351 is not designed for that, and it's jitter spec is 70 ps, which is
pretty noisy. It even has a spread spectrum mode that would be even worse.
They do have other parts designed for low jitter (< 1ps). Leo Bodnar's
GPSDOs with variable output clock frequencies are based on those chips and
they provide low phase noise, certainly enough for a radio.

Regards,

Mark


On Sun, Sep 16, 2018 at 10:22 AM, Chris Waldrup <***@gmail.com> wrote:

> How about using a ProgRock on Hans Summers QRP Labs website? This is a
> programmable crystal replacement.
>
> Chris
> KD4PBJ
>
> > On Sep 14, 2018, at 8:06 PM, paul swed <***@gmail.com> wrote:
> >
> > The beauty of a $2 arduino and a drop of code snitched from Engineer
> google.
> > OK enough of that back to the thread.
> > Regards
> > Paul
> > WB8TSL
> >
> >> On Fri, Sep 14, 2018 at 8:04 PM, Mike Feher <***@eozinc.com> wrote:
> >>
> >> Not when I built them in the late 60's and early 70's. All discrete. 73
> -
> >> Mike
> >>
> >>
> >>
> >> Mike B. Feher, N4FS
> >>
> >> 89 Arnold Blvd.
> >>
> >> Howell NJ 07731
> >>
> >> 848-245-9115
> >>
> >>
> >>
> >> -----Original Message-----
> >> From: time-nuts <time-nuts-***@lists.febo.com> On Behalf Of Richard
> >> (Rick) Karlquist
> >> Sent: Friday, September 14, 2018 7:15 PM
> >> To: Discussion of precise time and frequency measurement
> >> <time-***@lists.febo.com>; ed breya <***@telight.com>
> >> Subject: Re: [time-nuts] Programmable clock for BFO use....noise
> >>
> >>
> >>
> >>
> >>> Finally, of course, you can use DDS. This is nearly an ideal case for
> >>
> >>
> >>
> >> The trouble with a DDS is that you need a microcontroller with software
> >> just
> >> to baby sit the thing.
> >>
> >>
> >>
> >> Rick N6RK
> >>
> >>
> >>
> >> _______________________________________________
> >>
> >> time-nuts mailing list -- <mailto:time-***@lists.febo.com>
> >> time-***@lists.febo.com To unsubscribe, go to
> >> <http://lists.febo.com/mailman/listinfo/time-nuts_lists.febo.com>
> >> http://lists.febo.com/mailman/listinfo/time-nuts_lists.febo.com
> >>
> >> and follow the instructions there.
> >>
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Gerhard Hoffmann
2018-09-16 21:56:08 UTC
Permalink
Am 16.09.2018 um 20:00 schrub Mark Goldberg:
> For a radio BFO you want something with low phase noise (low jitter). The
> SI5351 is not designed for that, and it's jitter spec is 70 ps, which is
> pretty noisy. It even has a spread spectrum mode that would be even worse.
> They do have other parts designed for low jitter (< 1ps). Leo Bodnar's
> GPSDOs with variable output clock frequencies are based on those chips and
> they provide low phase noise, certainly enough for a radio

Oh, a half of a 12AX7 has always been good enough for my needs as a BFO,
xtal controlled or LC free running. 30 dB above the noise is S5, what more
do you want? The real problems of a receiver are IP3 and that you have
a preselector and a mixer that simply work without producing mess.
LO jitter is probably > 100 times more important than the BFO, that is just
for conversion of IF to audio.

cheers,
Gerhard, DK4XP

(I do not use many 12AX7 any more, in real life that is just a down
converter
block in a corner of of a Virtex FPGA. )


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Forrest Christian (List Account)
2018-09-15 03:31:34 UTC
Permalink
Would a mems oscillator such as a dsc6183 possibly work for you? I'm
uncertain if the characteristics of a mems oscillator is compatible with
your application.

For odd frequencies I often head toward a mems oscillator since many can be
programmed to any reasonable frequency. For example one can buy dsc6183
blanks and use a programmer to program it to your desired frequency.

The dsc61xx series happens to be one time programmable so you only get one
shot at it per blank. The programmer is relatively inexpensive, but might
be more than one would want to pay for a one off. I have found that having
a collection of blanks and a programmer is very useful since it allows me
to generate any frequency oscillator I need.

There are other mems oscillator models out there, with various specs and
programming (or not) options.






On Fri, Sep 14, 2018, 11:16 AM <***@cox.net> wrote:

> Off topic for this list, but you guys are experts in oscillator noise!
>
> Playing with some mechanical filters. Need USB and LSB crystals for the
> BFO. No one seems to make crystals anymore, especially in the 253 KHz
> range!
>
> Looking at the DigiKey Cardinal programmable oscillators. Cheap and
> available: CPPC1LZ A5B6
>
> Anyone have an idea how noisy these would be after a division by 4 to get
> them in range?
>
> Thanks,
>
> N0UU
> _______________________________________________
> time-nuts mailing list -- time-***@lists.febo.com
> To unsubscribe, go to
> http://lists.febo.com/mailman/listinfo/time-nuts_lists.febo.com
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>
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Adrian Godwin
2018-09-15 10:15:54 UTC
Permalink
Depending on the cost of those mems devices, a microcontroller can be so
trivial that you can just consider it as a smart eprom. Like Tom's PICDIV
dividers, which act more like perfect-for-pupose division chip than a micro.



On Sat, Sep 15, 2018 at 4:31 AM, Forrest Christian (List Account) <
***@packetflux.com> wrote:

> Would a mems oscillator such as a dsc6183 possibly work for you? I'm
> uncertain if the characteristics of a mems oscillator is compatible with
> your application.
>
> For odd frequencies I often head toward a mems oscillator since many can be
> programmed to any reasonable frequency. For example one can buy dsc6183
> blanks and use a programmer to program it to your desired frequency.
>
> The dsc61xx series happens to be one time programmable so you only get one
> shot at it per blank. The programmer is relatively inexpensive, but might
> be more than one would want to pay for a one off. I have found that having
> a collection of blanks and a programmer is very useful since it allows me
> to generate any frequency oscillator I need.
>
> There are other mems oscillator models out there, with various specs and
> programming (or not) options.
>
>
>
>
>
>
> On Fri, Sep 14, 2018, 11:16 AM <***@cox.net> wrote:
>
> > Off topic for this list, but you guys are experts in oscillator noise!
> >
> > Playing with some mechanical filters. Need USB and LSB crystals for the
> > BFO. No one seems to make crystals anymore, especially in the 253 KHz
> > range!
> >
> > Looking at the DigiKey Cardinal programmable oscillators. Cheap and
> > available: CPPC1LZ A5B6
> >
> > Anyone have an idea how noisy these would be after a division by 4 to get
> > them in range?
> >
> > Thanks,
> >
> > N0UU
> > _______________________________________________
> > time-nuts mailing list -- time-***@lists.febo.com
> > To unsubscribe, go to
> > http://lists.febo.com/mailman/listinfo/time-nuts_lists.febo.com
> > and follow the instructions there.
> >
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l***@cox.net
2018-09-15 04:20:00 UTC
Permalink
Got a whole bunch of answers all with useful info. I think I will go with Hans' 4 output board to see if the project works at all and go from there. Off on a three week tour of Italy to Malta and should have the parts when I get back. This is one of those weird design things so maybe the oscillators won't be the problem!

N0UU
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Pete Lancashire
2018-09-15 05:01:55 UTC
Permalink
Somebody send me the URL to that board thank you

On Fri, Sep 14, 2018, 9:21 PM <***@cox.net> wrote:

> Got a whole bunch of answers all with useful info. I think I will go
> with Hans' 4 output board to see if the project works at all and go from
> there. Off on a three week tour of Italy to Malta and should have the
> parts when I get back. This is one of those weird design things so maybe
> the oscillators won't be the problem!
>
> N0UU
> _______________________________________________
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ew via time-nuts
2018-09-15 11:09:18 UTC
Permalink
What about the application and the trigger circuit
In a message dated 9/15/2018 6:27:50 AM Eastern Standard Time, ***@kinali.ch writes:

On Fri, 14 Sep 2018 21:42:05 +0000
Bryan _ <***@outlook.com> wrote:

> I would be interested in hearing more of the more suitable classes of
> logic chips. I have a 20Mhz rubidium that I wanted to divide down to 10Mhz

Any logic family works, as long as it is fast enough to handle your
input frequency. Due to the non-linear (aka digital) behaviour
of a D-Flipflop style divider, it is recommended to use the slowest
possible logic family for the task. Otherwise the harmonics of the
switching of the FF will down-mix high frequency white noise down
to the signal band (this is the reason for the 10*log(N) noise scaling
of digital divider that Egan[1] and Calosso/Rubiola[2] and a few others
mentioned).

As a rule of thumb, I'd say that the FF should not be more than 10 to 20
times faster than the input frequency, to limit noise down-mixing.
If your FF is too fast or you want to reduce the noise floor, capacitively
loading and/or having some additional resistance in the Vcc and GND lines
will help slow it down. But ensure that the resistance is still low enough
that the FF's supply stays within specs at all time. Similarly, the
capacitive loading should be low enough that the output current is within
reasonable bounds.

Alternatively, using the Λ-divider approach[2] and introducing voltage
steps between 0 and 1 will also reduce down-mixing.

If you divide by something that is not a power of 2, then it is important
that each stage produces an output waveform with a 50% duty cycle. Otherwise
flicker noise which has been up-mixed by a previous stage, will be down-mixed
into the signal band, increasing the close-in phase-noise.


            Attila Kinali

[1] "Modeling Phase Noise in Frequency Dividers," by Egan, 1990

[2] "The Sampling Theorem in Pi and Lambda Digital Frequency Dividers,"
by Calosso and Rubiola 2013

--
<JaberWorky>    The bad part of Zurich is where the degenerates
                throw DARK chocolate at you.

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Attila Kinali
2018-09-15 12:34:47 UTC
Permalink
Hoi Bert,

On Sat, 15 Sep 2018 11:09:18 +0000 (UTC)
ew via time-nuts <time-***@lists.febo.com> wrote:

> What about the application and the trigger circuit

Sorry, I don't understand what you mean.

Attila Kinali

--
<JaberWorky> The bad part of Zurich is where the degenerates
throw DARK chocolate at you.

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ewkehren via time-nuts
2018-09-15 12:47:51 UTC
Permalink
The question was deviding a Rb  20 MHz to 10 that is easy to but how much effort is dependant what it is used for and that in turn determines what to use on the input. We have 4 choices depending on the requirementBert


Sent from my Galaxy Tab® A
-------- Original message --------From: Attila Kinali <***@kinali.ch> Date: 9/15/18 8:34 AM (GMT-05:00) To: Discussion of precise time and frequency measurement <time-***@lists.febo.com> Subject: Re: [time-nuts] Programmable clock for BFO use....noise
Hoi Bert,

On Sat, 15 Sep 2018 11:09:18 +0000 (UTC)
ew via time-nuts <time-***@lists.febo.com> wrote:

> What about the application and the trigger circuit

Sorry, I don't understand what you mean.

Attila Kinali

--
<JaberWorky> The bad part of Zurich is where the degenerates
                throw DARK chocolate at you.

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Didier Juges
2018-09-16 12:49:20 UTC
Permalink
Not the same part number but probably similar in terms of performance:

http://www.ko4bb.com/getsimple/index.php?id=microprocessor-crystal-oscillator-comparison

Bottom line: use a true crystal oscillator, or make your own PLL, not a
programmable "microprocessor crystal"

On Fri, Sep 14, 2018, 11:15 AM <***@cox.net> wrote:

> Off topic for this list, but you guys are experts in oscillator noise!
>
> Playing with some mechanical filters. Need USB and LSB crystals for the
> BFO. No one seems to make crystals anymore, especially in the 253 KHz
> range!
>
> Looking at the DigiKey Cardinal programmable oscillators. Cheap and
> available: CPPC1LZ A5B6
>
> Anyone have an idea how noisy these would be after a division by 4 to get
> them in range?
>
> Thanks,
>
> N0UU
> _______________________________________________
> time-nuts mailing list -- time-***@lists.febo.com
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>
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Bob kb8tq
2018-09-16 15:48:29 UTC
Permalink
Hi

Coming back to the basics of the design:

If you are playing with a normal radio, a BFO that drifts under a few Hertz is
going to be pretty much un-noticable. Drift is a bit of an elastic term in this case
since it can cover a bunch of different parameters on an oscillator (temperature
as things warm up / aging / retrace / voltage stability ….).

For fun, lets say that 25.3 Hz over a day and 5C is “adequate” for the task. Oddly
enough this makes the math easy. 25.3 Hz / 253 KHz = 1 / 10,000 = 100 ppm.

A crystal that drifts 1 ppm / C is not a super duper part at room temperature. Over
our 5C range, that’s only 5 ppm. It would have to be 10X worse to really eat into
our budget.

Aging / warmup / retrace wise, a crystal that moves a couple ppm in the first day
is moving a lot. Again not a big hit to our budget.

Voltage stability on a properly designed circuit with a normal voltage regulator should
be very small compared to the budget. Maybe it’s a ppm, probably less.

Bottom line - the crystal likely is doing >10X better than what our arbitrary spec would
require. That’s why a lot of radios do just fine with an L/C based BFO.

For even more fun, take a look at the likely drift of the mechanical filters involved. They
are not going to be as stable as the crystal ….. Even a crystal filter at 250KHz isn’t
going to be as stable as the AT cut based evaluation above.

Bob


> On Sep 16, 2018, at 7:49 AM, Didier Juges <***@gmail.com> wrote:
>
> Not the same part number but probably similar in terms of performance:
>
> http://www.ko4bb.com/getsimple/index.php?id=microprocessor-crystal-oscillator-comparison
>
> Bottom line: use a true crystal oscillator, or make your own PLL, not a
> programmable "microprocessor crystal"
>
> On Fri, Sep 14, 2018, 11:15 AM <***@cox.net> wrote:
>
>> Off topic for this list, but you guys are experts in oscillator noise!
>>
>> Playing with some mechanical filters. Need USB and LSB crystals for the
>> BFO. No one seems to make crystals anymore, especially in the 253 KHz
>> range!
>>
>> Looking at the DigiKey Cardinal programmable oscillators. Cheap and
>> available: CPPC1LZ A5B6
>>
>> Anyone have an idea how noisy these would be after a division by 4 to get
>> them in range?
>>
>> Thanks,
>>
>> N0UU
>> _______________________________________________
>> time-nuts mailing list -- time-***@lists.febo.com
>> To unsubscribe, go to
>> http://lists.febo.com/mailman/listinfo/time-nuts_lists.febo.com
>> and follow the instructions there.
>>
> _______________________________________________
> time-nuts mailing list -- time-***@lists.febo.com
> To unsubscribe, go to http://lists.febo.com/mailman/listinfo/time-nuts_lists.febo.com
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l***@cox.net
2018-09-16 20:21:08 UTC
Permalink
Just the info I wanted! Thanks, N0UU

> On September 16, 2018 at 8:49 AM Didier Juges <***@gmail.com> wrote:
>
> Not the same part number but probably similar in terms of performance:
>
> http://www.ko4bb.com/getsimple/index.php?id=microprocessor-crystal-oscillator-comparison
>
> Bottom line: use a true crystal oscillator, or make your own PLL, not a programmable "microprocessor crystal"
>
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ewkehren via time-nuts
2018-09-17 10:25:48 UTC
Permalink
Good choice                    Bert Kehren


Sent from my Galaxy Tab® A
-------- Original message --------From: Gerhard Hoffmann <***@arcor.de> Date: 9/16/18 6:30 PM (GMT-05:00) To: time-***@lists.febo.com Subject: Re: [time-nuts] Programmable clock for BFO use....noise


Am 16.09.2018 um 23:11 schrieb Attila Kinali:
> On Sun, 16 Sep 2018 22:08:19 +0200
> Gerhard Hoffmann <***@arcor.de> wrote:
>
>> I'm also not a fan of using slowish, slew-rate challenged  logic as a
>> replacement
>> for a low pass. When I want a low pass, I make it from nice,
>> time-invariant RLC.
> Unfortunately, using a low pass after the divider will not
> prevent the down-mixing. The down-mixing happens as an inherent
> property of digital circuits. Any filtering you do afterwards
> will be too late. If you want to have low noise, then the only
> way is to produce a non-square wave signal. Or in other words:
> use a divider built from harmonic mixers*.
Why do you assume that slew-rate limited mixers are any
better than mixers with an ultra-short analog time window
for doing mess?

We should sort that out offline, we are just 20 miles apart?
I propose the Zwickel pub in Dudweiler; I'm there with the
mostly emerited Fraunhofer people on Friday evenings
now & then.        :-)  :-)  :-)
> * That is, if you don't like Λ-dividers or DDS
I do like DDS, and I don't see  a reason for the D/A converters
in front of the mixers. D/A converters remove the fun when you
can just instantiate a multiplier.

Cheers,

Gerhard



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