Discussion:
femtosecond jitter
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John Larkin
2018-04-13 15:54:41 UTC
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If you walk the differential data and clock inputs of an NB7V52  CML
flipflop across one another in time, the equivalent jitter is below 20
fs RMS. That's what we're measuring, but our test rig may well dominate
the jitter, so the flop is probably better.

We're using this to test the jitter of some of our timing products, with
1/10 the noise floor and 1e-4 times the cost of other ways to do it.

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John Larkin, President
Highland Technology, Inc
18 Otis Street
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phone 415 551-1700 fax 551-5129
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http://www.highlandtechnology.com

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Bruce Griffiths
2018-04-14 02:06:30 UTC
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Thus a DDMTD using NB7V52's as the mixers should have useful performance

Bruce
If you walk the differential data and clock inputs of an NB7V52 CML
flipflop across one another in time, the equivalent jitter is below 20
fs RMS. That's what we're measuring, but our test rig may well dominate
the jitter, so the flop is probably better.
We're using this to test the jitter of some of our timing products, with
1/10 the noise floor and 1e-4 times the cost of other ways to do it.
https://www.dropbox.com/s/1i2yz7otty94o9l/NB7_Jitter_1.jpg?raw=1
https://www.dropbox.com/s/qahpb8uh1xr53vj/NB7_Steps.jpg?raw=1
https://www.dropbox.com/s/tpphhi79yxgzy34/NB7_tc.jpg?raw=1
--
********************************** arb
John Larkin, President
Highland Technology, Inc
18 Otis Street
San Francisco, CA 94103
phone 415 551-1700 fax 551-5129
http://www.highlandtechnology.com
This is a Highland Technology confidential communication
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Magnus Danielson
2018-04-14 12:59:04 UTC
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John,

How where these measurements done?
Also, it looks like you have a systematic component in there, about 80
fs guestimating from the plot creating essentially two tracks up the
slope that is the tell-tale of a sinuoid phase modulation of some source.

Considering the temperature stability that you nicely plotted as a
quadratic shape, it seems like a good thermal stability is needed, which
comes as no big chock.

Can do you do a longer measurement and accumulate the data in a
2D-histogram fashion? That is count occurrences for the amplitude/time
position and then color code it accordingly? That have proved to be a
good tool for analysis.

Cheers,
Magnus
Post by John Larkin
If you walk the differential data and clock inputs of an NB7V52  CML
flipflop across one another in time, the equivalent jitter is below 20
fs RMS. That's what we're measuring, but our test rig may well dominate
the jitter, so the flop is probably better.
We're using this to test the jitter of some of our timing products, with
1/10 the noise floor and 1e-4 times the cost of other ways to do it.
https://www.dropbox.com/s/1i2yz7otty94o9l/NB7_Jitter_1.jpg?raw=1
https://www.dropbox.com/s/qahpb8uh1xr53vj/NB7_Steps.jpg?raw=1
https://www.dropbox.com/s/tpphhi79yxgzy34/NB7_tc.jpg?raw=1
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John Larkin
2018-04-14 16:45:10 UTC
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Hi, Magnus,

We did a little PC board that has two Analog Devices CML comparators
that feed the flop.

  https://www.dropbox.com/s/05ti1c57eush0uq/99S394A.pdf?dl=0

An external DAC tweaks the VBIAS voltage to slew the edge times across
one another, and an external ADC looks at the averaged flop outputs. The
jitter noise floor is probably dominated by the test signals, not the
flop under test. We considered something like a micrometer-driven
differential trombone line... note that 1 fs is one PPM of a nanosecond,
how far light travels in 12 micro-inches.

The quantization is probably DAC resolution. The step function is just
the integral of the histogram.

This is going into a test set that needs maybe 1 ps RMS noise floor, so
this flop is hugely better than what we need. It's a big deal to set
this up, so I don't think we'll do any more measurements.

As a bang-bang phase detector, with some lowpass filtering in the loop,
this flop would have a noise floor in the attosecond range. You're
right, temperature will dominate low-frequency noise, and not just in
the flop.

John
Post by Magnus Danielson
John,
How where these measurements done?
Also, it looks like you have a systematic component in there, about 80
fs guestimating from the plot creating essentially two tracks up the
slope that is the tell-tale of a sinuoid phase modulation of some source.
Considering the temperature stability that you nicely plotted as a
quadratic shape, it seems like a good thermal stability is needed, which
comes as no big chock.
Can do you do a longer measurement and accumulate the data in a
2D-histogram fashion? That is count occurrences for the amplitude/time
position and then color code it accordingly? That have proved to be a
good tool for analysis.
Cheers,
Magnus
Post by John Larkin
If you walk the differential data and clock inputs of an NB7V52  CML
flipflop across one another in time, the equivalent jitter is below 20
fs RMS. That's what we're measuring, but our test rig may well dominate
the jitter, so the flop is probably better.
We're using this to test the jitter of some of our timing products, with
1/10 the noise floor and 1e-4 times the cost of other ways to do it.
https://www.dropbox.com/s/1i2yz7otty94o9l/NB7_Jitter_1.jpg?raw=1
https://www.dropbox.com/s/qahpb8uh1xr53vj/NB7_Steps.jpg?raw=1
https://www.dropbox.com/s/tpphhi79yxgzy34/NB7_tc.jpg?raw=1
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--
********************************** arb

John Larkin, President
Highland Technology, Inc
18 Otis Street
San Francisco, CA 94103

phone 415 551-1700 fax 551-5129
***@highlandtechnology.com
http://www.highlandtechnology.com

This is a Highland Technology confidential communication

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Magnus Danielson
2018-04-15 21:17:14 UTC
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Hi,
Post by John Larkin
Hi, Magnus,
We did a little PC board that has two Analog Devices CML comparators
that feed the flop.
  https://www.dropbox.com/s/05ti1c57eush0uq/99S394A.pdf?dl=0
An external DAC tweaks the VBIAS voltage to slew the edge times across
one another, and an external ADC looks at the averaged flop outputs. The
jitter noise floor is probably dominated by the test signals, not the
flop under test.
Ah, thanks. Much clearer now!

You more tweak the voltage than actual timing, it's the slope property
that does the timing, but interesting never the less.
Post by John Larkin
We considered something like a micrometer-driven
differential trombone line... note that 1 fs is one PPM of a nanosecond,
how far light travels in 12 micro-inches.
Yeah, that would be "interesting" and maybe more work than you wanted to
game for.
Post by John Larkin
The quantization is probably DAC resolution. The step function is just
the integral of the histogram.
Sure.
Post by John Larkin
This is going into a test set that needs maybe 1 ps RMS noise floor, so
this flop is hugely better than what we need. It's a big deal to set
this up, so I don't think we'll do any more measurements.
For that needed precision, this seems not to be your limiting factor,
for sure. Good work.

OK. it would have been interesting to characterize it further.
Post by John Larkin
As a bang-bang phase detector, with some lowpass filtering in the loop,
this flop would have a noise floor in the attosecond range. You're
right, temperature will dominate low-frequency noise, and not just in
the flop.
Yes. With both sensor and steering you can temperature compensate it.
With modest thermal isolation you can keep changes slow enough for
compensation to have a chance.

Cheers,
Magnus
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John Larkin
2018-04-16 15:31:17 UTC
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Post by Magnus Danielson
Hi,
Post by John Larkin
Hi, Magnus,
We did a little PC board that has two Analog Devices CML comparators
that feed the flop.
  https://www.dropbox.com/s/05ti1c57eush0uq/99S394A.pdf?dl=0
An external DAC tweaks the VBIAS voltage to slew the edge times across
one another, and an external ADC looks at the averaged flop outputs. The
jitter noise floor is probably dominated by the test signals, not the
flop under test.
Ah, thanks. Much clearer now!
You more tweak the voltage than actual timing, it's the slope property
that does the timing, but interesting never the less.
Downstream of the comparators, all the flop sees is time... not voltage
shift. We used a sampling scope to calibrate the picoseconds-per-volt
slope of the voltage input from the DAC.
--
********************************** arb

John Larkin, President
Highland Technology, Inc
18 Otis Street
San Francisco, CA 94103

phone 415 551-1700 fax 551-5129
***@highlandtechnology.com
http://www.highlandtechnology.com

This is a Highland Technology confidential communication

_______________________________________________
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Attila Kinali
2018-04-14 14:36:45 UTC
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On Fri, 13 Apr 2018 08:54:41 -0700
Post by John Larkin
If you walk the differential data and clock inputs of an NB7V52  CML
flipflop across one another in time, the equivalent jitter is below 20
fs RMS. That's what we're measuring, but our test rig may well dominate
the jitter, so the flop is probably better.
I heard similar numbers for the NB7V52 last week at EFTF. So you
cannot be that far off.

Attila Kinali
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throw DARK chocolate at you.
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